• Title/Summary/Keyword: 합성 모듈러 시스템

검색결과 18건 처리시간 0.027초

Design of Systolic Array for Fast RSA Modular Multiplication (고속 RSA 모듈러 곱셈을 위한 시스톨릭 어레이의 설계)

  • Kang, Min-Sup;Nam, Sung-Yong
    • Proceedings of the Korea Information Processing Society Conference
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    • 한국정보처리학회 2002년도 춘계학술발표논문집 (하)
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    • pp.809-812
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    • 2002
  • 본 논문은 RSA 암호시스템에서 고속 모듈러 곱셈을 위한 최적화된 시스톨릭 어레이의 설계를 제안한다. 제안된 방법에서는 미리 계산된 가산결과를 사용하여 개선된 몽고메리 모듈러 곱셈 알고리듬을 제안하고, 고속 모듈러 곱셈을 위한 새로운 구조의 시스톨릭 어레이를 설계한다. 미리 계산된 가산결과를 얻기 위해 CLA(Carry Look-ahead Adder)를 사용하였으며, 이 가산기는 덧셈연산에 있어서 캐리전달 지연이 제거되므로 연산 속도를 향상 시킬 수 있다. 제안된 시스톨릭 구조는VHDL(VHSlC Hardware Description Language)을 사용하여 동작적 수준을 기술하였고, Ultra 10 Workstation 상에서 $Synopsys^{TM}$ 툴을 사용하여 합성 및 시뮬레이션을 수행하였다. 또한, FPGA 구현을 위하여 Altera MaxplusII를 사용하여 타이밍 시뮬레이션을 수행하였고, 실험을 통하여 제안한 방법을 효율성을 확인하였다.

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Evaluation on Flexural Performance for Light-Weight Composite Floor with Sound Reduction System (층간소음 대응형 경량합성바닥판에 대한 휨성능 평가)

  • Bae, Kyu Woong;Lee, Sang Sup;Park, Keum Sung;Heo, Byung Wook;Hong, Sung Yub
    • Journal of Korean Society of Steel Construction
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    • 제26권3호
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    • pp.241-250
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    • 2014
  • The purpose of this study is to propose structural technologies on the light-weight composite floor systems in the unit modular and to evaluate structural performance of the composite floor through flexural experiments. The flexural experiments were carried out on total nine specimens(each three type in shape) using steel flat deck and truss deck. From the results of test, all specimens showed the same failure patterns which exhibited deflection at the center of the specimens due to flexural deformation before concrete crushing at the upper of specimens. Also, we know that the proposed floors satisfied in serviceability and would be safe sufficiently. The ratio of experimental yield load by theoretical nominal load was the distribution of 0.86 to 1.27 with an average 1.04. Coefficient of variation in distribution showed good agreement.

Design and FPGA Implementation of a High-Speed RSA Algorithm for Digital Signature (디지털 서명을 위한 고속 RSA 암호 시스템의 설계 및 FPGA 구현)

  • 강민섭;김동욱
    • The KIPS Transactions:PartC
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    • 제8C권1호
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    • pp.32-40
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    • 2001
  • In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

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A Scalable ECC Processor for Elliptic Curve based Public-Key Cryptosystem (타원곡선 기반 공개키 암호 시스템 구현을 위한 Scalable ECC 프로세서)

  • Choi, Jun-Baek;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • 제25권8호
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    • pp.1095-1102
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    • 2021
  • A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when NPE=1, and with 203 kGEs and 12.8 kbits of RAM when NPE=8. The performance of sECCP with NPE=1 and NPE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.

A Study on the Minimum Error Entropy - related Criteria for Blind Equalization (블라인드 등화를 위한 최소 에러 엔트로피 성능기준들에 관한 연구)

  • Kim, Namyong;Kwon, Kihyun
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • 제2권3호
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    • pp.87-95
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    • 2009
  • As information theoretic learning techniques, error entropy minimization criterion (MEE) and maximum cross correntropy criterion (MCC) have been studied in depth for supervised learning. MEE criterion leads to maximization of information potential and MCC criterion leads to maximization of cross correlation between output and input random processes. The weighted combination scheme of these two criteria, namely, minimization of Error Entropy with Fiducial points (MEEF) has been introduced and developed by many researchers. As an approach to unsupervised, blind channel equalization, we investigate the possibility of applying constant modulus error (CME) to MEE criterion and some problems of the method. Also we study on the application of CME to MEEF for blind equalization and find out that MEE-CME loses the information of the constant modulus. This leads MEE-CME and MEEF-CME not to converge or to converge slower than other algorithms dependent on the constant modulus.

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The Implementation of Communication Emulate Based on Component For Automation System (자동화시스템을 위한 컴포넌트 기반의 통신 Emulate 구현)

  • Jeong Hwa-Young
    • Journal of Digital Contents Society
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    • 제3권2호
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    • pp.245-254
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    • 2002
  • Currently, communication field for automation system can be divided by simple serial communication for communication between each internal devices and network base remote control system that is based on TCP/IP. In spite of great development of network, communication part for internal control is using simple RS232 base until present. Also, development techniques of system developed by object oriented program in modular programming techniques of each function unit. Currently, it developed by component base development technique that is parts unit of software. This is presented by the new alternative of software development techniques as techniques to composition independent operation unit including business logic and is connected to development of new system. Therefore, this research implemented internal communication Emulate in RS232C based on GUI that apply development techniques of component base. that is, I maked component to commnication control part between receiving and sending and, as composite it, Control part did to handling between send and receive data.

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Nonlinear Behavior of Composite Modular System's Joints (합성 모듈러 시스템 접합부의 비선형 거동 평가)

  • Choi, Young hoo;Lee, Jong il;Lee, Ho chan;Kim, Jin koo
    • Journal of the Earthquake Engineering Society of Korea
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    • 제25권4호
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    • pp.153-160
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    • 2021
  • The connection of the steel structure serves to transmit external forces to the main components. The same is true for the behavior of modular systems composed mainly of steel or composite members. In this study, the joint performance of the composite and steel modules proposed was evaluated. The analytical models of the two joint types were constructed and were subjected to cyclic loading to assess the safety and the energy dissipation capacity of the joint types. The analysis results of the joints showed that the joints of the modular systems remain stable when the joint rotation reached the seismic performance limit state of the 0.02 rad required for steel intermediate moment frame. It was also observed that the joint of the composite modular system showed higher energy dissipation capacity compared with the steel modular system.

Design of a ECC arithmetic engine for Digital Transmission Contents Protection (DTCP) (컨텐츠 보호를 위한 DTCP용 타원곡선 암호(ECC) 연산기의 구현)

  • Kim Eui seek;Jeong Yong jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제30권3C호
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    • pp.176-184
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    • 2005
  • In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.