• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.8
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• pp.582-594
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• 2016

Most studies on hybrid buses are on large-sized buses and not mid-sized low-floor buses. This study uses MATLAB simulation to evaluate the fuel efficiency of such buses powered by diesel. Based on the results, a hybrid electric vehicle system is recommended for the best combination of power and gear ratio. A parallel hybrid system was selected for the hybridization, which transmits front and rear wheel power independently. The necessary power to satisfy the target performance was calculated, and the applicable capacity area was designed. Dynamic programing was used to create and optimize a component sizing algorithm, which was used to scale the capacity of each component of the power source to satisfy the design criteria. The fuel efficiency rate, optimum power source capacity, and gear ratio can be improved by converting a conventional bus into a parallel hybrid bus.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.8
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• pp.773-779
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• 2011

In order to improve fuel economy and emissions, many studies of HEV have been conducted. However, most of these studies concentrate on parallel or power-split HEVs. Series-type HEVs have some advantages over parallel and power-split HEVs. One is that the engine is operated at high efficiency since the engine and the driveshaft are decoupled. Nevertheless, the optimization of the powertrain system of series HEV has not been specifically addressed. We conduct an optimization of the generation system of a series HEV based on the series HEV bus. The main objectives are to simulate the system and to compare the fuel economies of conventional and optimized generation systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.69-74
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• 2009

We propose the novel Hybrid bus arbitration policy that prevents starvation phenomenon presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitration policies. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and design overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others in the aspect of design complexity, timing margin, bus utilization, starvation prevention, request cycle and so on.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.46-51
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• 2010

We propose the novel Hybrid bus arbitration policy that prevents a priority monopolization presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitrations. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and area overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others and effectively controls the bus utilization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6C
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• pp.594-599
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• 2007

In this paper, we present new representation of DCT/DFT matrices via one hybrid architecture. Based on a element inverse matrix factorization algorithm, we show that the DCT and DFT have a same recursive computational pattern, and we can develop an hybrid architecture by using some diagonal matrices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.50-56
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.

• Korea Petroleum Association Journal
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• s.276
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• pp.46-49
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• 2010

• Korea Petroleum Association Journal
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• s.281
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• pp.43-48
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• 2011

• KIPE Magazine
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• v.12 no.5
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• pp.24-30
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• 2007