• The Journal of the Acoustical Society of Korea
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• v.14 no.5
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• pp.63-73
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• 1995

The conventional acoustic sounds can be synthesized by Frequency Modulation which includes the variation of frequency, amplitude, and modulation index. In this paper the number of variable synthesis parameters are limited to easily implement the existing two carrier FM algorithm by hardware. The DSP(Digital Signal Processor), which is able to carry out the modified algorithm and synthesize 16 sounds at a time, is designed with $0.8{\mu}m$ standard sells. The DSP which can synthesize 2 sounds at a time is implemented by ASIC emulator to examine the sound quality of the designed DSP. Through the objective and subjective estimation, it is confirmed that the sounds of many instruments from the implemented DSP are very closed to their real sound. Finally the designed DSP is layouted and simulated by VLSI desgn tool. According to the simulation, the designed DSP has the sufficiently fast speed for synthesizing 16 sounds at a time.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.538-540
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• 2004

본 연구는 컴퓨터 연산을 위한 하드웨어 설계에서 고성능 연산에 사용되는 케리-세이브 가산기 (Carry-save adder) 합성에 관한 연구이다. 기존의 연구에서는, 연산 합성 문제와 합성된 연산의 배치 문제를 두개의 연속된 독립된 두개의 문제로 간주하고 풀었지만, 본 연구에서는 연산 합성 과정에서 연산 배치를 고려한 통합된 방법을 제시하여 전체적인 최적화된 결과를 얻었다. 연결선 상에서의 전력 소모나 지연시간이 점점 더 중요해지는 시스템-온-칩 (system-on-chip) 설계에서 본 연구의 통합적인 설계 방법은 매우 긴요하며 앞으로 효과적으로 이용될 수 있을 것이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.767-773
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• 2017

In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

• Journal of IKEEE
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• v.25 no.1
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• pp.10-14
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• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.738-740
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• 1998

플래곤-랜더링을 위한 영상합성 구조는 지역 프레임버퍼와 메모리 비용이 큰 문제점을 가진다. 이를 개선하기 위해서 화면-분할 방법과 가상 지역 프레임버퍼 방법이 도입되었으나 이 방법들 역시 상당한 메모리 비용이 요구된다. 본 논문에서는 지역 프레임버퍼 메모리 비용 측면에서 효율적이고, 영상 합성에 필요한 하드웨어를 제거하며, 동시에 영상 합성 시간을 숨길 수 있는 랜더링 시스템과 이에 필요한 병렬 래스터라이져를 설계한다.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.73-76
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• 2003

본 논문에서는 MPEG-2 BC와 AAC의 복호화 과정 중 함성 필터링 과정의 알고리듬을 분석하여 공동된 구조로 연산을 수행한 수 있는 광용 합성 필터 구조에 대하여 논하였다. 제안된 공용 합성 필터 구조는 Regressive 구조를 이용하여 MPEG-2 BC와 AAC의 복호화를 효과적으로 공용 수행하도록 하였다. 제안한 구조는 FFT를 사용할 경우에 필요한 전처리 및 후처리 과정을 고려해주지 않아도 되고 복소수 연산이 아닌 실수연산이 되어 하드웨어 구조가 단순하게 된다. 또한 MPEG-2 AAC의 다양한 윈도우 변환에도 안정적으로 연산되는 구조임을 확인하였다.

• The Journal of the Acoustical Society of Korea
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• v.17 no.3
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• pp.27-36
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• 1998

현재 상용화된 사운드 합성 기기에서 널리 쓰이고 있는 PCM 방식에서의 문제점은 고음질의 음을 얻기 위해서 많은 메모리 용량을 필요로 하는 것이다. 이 논문에서는 이 문 제를 해결하기 위해 MPEG 오디오 압축 방식을 적용하여 샘플된 음을 압축하고, 실시간으 로 이를 복호화 해서 음을 합성해내는 사운드 합성 시스템을 설계하였다. 사운드 합성 시스 템은 마이크로프로세서, 음원 DSP, MPEG 오디오 복호화기로 구성되며, 44.1Khz의 샘플링 주파수로 32개의 음을 동시에 합성할 수 있도록 설계되었다. 설계 과정에서 각각의 기능 요 소를 C언어로 기술하여 사운드 합성 시스템에 대한 소프트웨어 모델을 작성하였다. 이것을 통해 미리 전체 시스템의 동작을 시뮬레이션하고, 압축 방식을 적용함으로써 발생될 수 있 는 여러 가지 문제점에 대한 해결 방안을 제시하였다. 시뮬레이터로 시스템의 동작을 검증 한 후, DSP와 MPEG 복호화기를 포함하는 사운드 합성 시스템을 VHDL로 설계하여 시뮬 레이션을 통해 하드웨어가 정상적으로 동작함을 확인하였다. MPEG 오디오 압축 방식을 이 용함으로써 메모리 용량 측면에서는 약8:1의 감소 효과를 얻을 수 있다.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.619-633
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• 1993

A new High level hardware Description Language, ASPHODEL(Algorithm Synthesis Pascal Hardware for Optimal Design and Efficient Language), and its algorithm compiler for high level synthesis are described in this paper. The new HDL, appropriated to the description of algorithmic level and lower, models VLSI circuits as an abstracted block which is consisted of input/output ports and hierachical processors to control VLSI complexities with efficiency. Also, in order to improve the descriptive power, popular Pascal programming language is modified to build ASPHODEL syntax rules. ASPHODEL algorithm compiler generates an intermediate form through lexical and syntax analysis from ASPHODEL source codes. To show the validation of presented language and its compiler, those are applied to practical design examples.