• Journal of Korean Society of Transportation
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• v.19 no.5
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• pp.71-83
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• 2001

This paper introduces the simulation system which was developed to evaluate the effectiveness of ITS, and presents its adaptabilities to traffic signal control systems. The simulation system in this paper has a function of real-time testing and evaluating traffic control systems. It consists of Modu-RE which is a simulation operating software and Real-CID which is a controller interface device. Real-CID allows Modu-RE to communicate with traffic control hardware.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.579-585
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• 2003

Recently most of 3D graphics rendering Processors have the pixel cache storing depth data and color data to reduce the memory latency and the bandwidth requirement. In this paper, we propose the effective pixel cache for improving the performance of a rendering processor. The proposed cache system stores the depth data selectively based on the result of Z-test and the color data are stored into the auxiliary buffer. Simulation results show that the 16Kbyte proposed cache system provides better performance than the 32Kbyte conventional cache.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of Korea Multimedia Society
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• v.16 no.2
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• pp.226-233
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• 2013

Self-diagnosis, regular examination, completion examination and precise safety examination on an elevator offer primary sources for evaluating performance and stability of the elevator. as critical examination for operating the elevator. The items on vibration of an elevator in the self-diagnosis and safety examination are not especially specified but vibration itself is considered as essential element to provide diverse analysis data. There is the equipment "EVA-625" for measuring vibration of an elevator. It is operated by reading data via computer and analyzing data by skilled engineer. This study aims to design and realize software to analyze data collected through the LabVIEW, a graphic program language and hardware for receiving data measuring vibration of an elevator by using 3-Axis acceleration sensor.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.469-474
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• 2009

This paper proposes an real time ray tracing system using optimized kd-tree traversal environment and ray/triangle intersection algorithm. The previous kd-tree traversal algorithms search for the upper nodes in a bottom-up manner. In a such way we need to revisit the already visited parent node or use redundant memory after failing to find the intersected primitives in the leaf node. Thus ray tracing for relatively complex scenes become more difficult. The new algorithm contains stacks implemented on GPU's local memory on CUDA framework, thus elegantly eliminate the problems of previous algorithms. After traversing the node we perform the latest CPU-based ray/triangle intersection algorithm 'Plucker coordinate test', which is further accelerated in massively parallel thanks to CUDA. Plucker test can drastically reduce the computational costs since it does not use barycentric coordinates but only simple test using the relations between a ray and the triangle edges. The entire system is consist of a single ray kernel simply and implemented without introduction of complicated synchronization or ray packets. Consequently our experiment shows the new algorithm can is roughly twice as faster as the previous.

• The Journal of the Korea Contents Association
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• v.9 no.4
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• pp.247-253
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• 2009

PACS(Picture archiving communication system) is a system that enables medical images such as X -ray, CT, MRI, PET to be stored electronically viewed on computer screens so that doctors and other authorized people can access search the information as needed. But if they are not in hospital area for example on holiday or at night, that are not able to access the PACS system instantly. We have to solve this problem for more efficient patient care. So we try to suggest a method that use the PDA system that wireless LAN and CDMA cellular phone are equipped. This system may help to access easier to PACS system regardless of the location and can also attribute the development of telemedicne.

• Journal of the Korea Computer Graphics Society
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• v.8 no.2
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• pp.9-14
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• 2002

In cases of densely occluded urban scenes, it is effective to determine the visibility of scenes, since only small parts of the scene are visible from a given cell. In this paper, we introduce a new visibility preprocessing method that efficiently computes potentially visible objects for volumetric cells. The proposed method deals with general 3D polygonal models and invisible objects jointly blocked by multiple occluders. The proposed approach decomposes volume visibility into a set of point visibilities, and then computes point visibility using hardware visibility queries, in particular HP_occlusion_test and NV_occlusion_query. We carry out experiments on various large-scale scenes, and show the performance of our algorithm.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.01a
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• pp.225-228
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• 2011

핸드폰에 의한 모바일 콘텐츠의 사용량이 날로 증가하고 있으며 이러한 추세에 맞추어 다양한 콘텐츠들이 다양한 플렛폼에서 생산되고 있다. 모바일 플랫폼에서 사용 가능한 콘텐츠 생산성은 플랫폼의 특수성으로 인해 생산 속도가 느리고 인력 투입이 많은 것이 문제점으로 지적되고 있다. 또한 무선 플랫폼에서 사용 가능한 콘텐츠 제작시 다양한 하드웨어 플랫폼으로 인한 액정 크기의 다양성과 사용 가능한 콘텐츠 개발 언어의 다양성으로 인한 문제점도 많은 것으로 알려져 있다. 본 연구에서는 이러한 생산성 저하의 원인으로 대표되는 문제점들과 다양한 하드웨어 플랫폼으로 인해 발생하는 문제점들을 해결하기 위한 모바일 콘텐츠를 통합 제작하고 테스트하는 PC용 소프트웨어를 개발하였다. xHTML 언어로 제작된 모바일 콘텐츠를 다양한 언어로 변환하기 위하여 패턴매칭 알고리즘을 사용한 변환 모듈을 개발하였다. 또한, 변환된 콘텐츠들을 각 플랫폼별로 테스팅 하기 위하여 개발자의 직접적 개입이 없이 모든 콘텐츠를 자동으로 검사하고 결과를 리포트 생성하는 자동 테스트 부분과 개발자의 육안으로 확인하고 테스트하여 결과 리포트를 생성하는 수동 테스트 부분으로 나누어진 소프트웨어 엔진을 개발하였다. 이상의 변환엔진을 사용하여 xHTML로 제작한 원본 콘텐츠는 다양한 플랫폼에서 이용 가능한 콘텐츠로 생산이 용이해 졌으며, 두 테스트 엔진을 사용하여 기본적인 콘텐츠 오류들을 쉽게 찾아내고 수정할 수 있는 개발 환경을 구축하였다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.10
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• pp.831-835
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• 2020

By automatically generating HDL codes from C/C++ source codes, HLS makes it possible to shorten FPGA system developing period through easy timing control and structure change. We designed LDPC encoder for telemetry standard 106-17 with Xilinx Vivado HLS and showed hardware structure can be easily adapted for different purposes through minor C code modification. Synthesis results targeting Spartan-7 xc7s100 device are presented for throughput and hardware complexity comparison.