Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

A Pixel Cache Architecture with Selective Loading Scheme based on Z-test

깊이 검사 결과에 의한 선택적 적재 방법을 가지는 픽셀 캐쉬 구조

  • 이길환 (연세대학교 컴퓨터과학과) ;
  • 박우찬 (세종대학교 컴퓨터공학부) ;
  • 김일산 (연세대학교 컴퓨터과학과) ;
  • 한탁돈 (연세대학교 컴퓨터과학과)
  • Published : 2003.10.01
Download PDF
⟨ Previous Next ⟩

Abstract

Recently most of 3D graphics rendering Processors have the pixel cache storing depth data and color data to reduce the memory latency and the bandwidth requirement. In this paper, we propose the effective pixel cache for improving the performance of a rendering processor. The proposed cache system stores the depth data selectively based on the result of Z-test and the color data are stored into the auxiliary buffer. Simulation results show that the 16Kbyte proposed cache system provides better performance than the 32Kbyte conventional cache.

최근 대부분의 3차원 그래픽 렌더링 프로세서는 메모리 접근 지연 및 대역폭을 줄이기 위해 깊이 데이타와 색상 데이타를 가지고 있는 픽셀 캐쉬(pixel cache)를 사용한다. 본 논문에서는 렌더링 프로세서의 성능을 향상시키기 위한 효과적인 픽셀 캐쉬 구조를 제시한다. 제안하는 픽셀 캐쉬 시스템은 기본적으로 3차원 렌더링 프로세서에서 수행되는 깊이 검사(Z-test) 결과에 의해 선택적으로 깊이 데이터를 캐쉬에 저장하며, 색상 데이타는 별도의 버퍼에 저장한다. 시뮬레이션 결과에 의하면 16K바이트의 제안하는 캐쉬 시스템이 32K바이트의 일반적인 캐쉬보다 더 나은 성능을 보인다.

Keywords

References

  1. Z.S. Hakura and A. Gupta, 'The design and analysis of a cache architecture for texture mapping,' Proceedings of the 24th International Symposium on Computer Architecture, pp. 108120, June 1997 https://doi.org/10.1145/264107.264152
  2. H. Igehy, M. Eldridge, and K. Proudfoot, 'Prefetching in a texture cache architecture,' Proceedings of 1998 SIGGRAPH/Eurographics Workshop on Graphics Hardware, pp. 133-142, Aug. 1998 https://doi.org/10.1145/285305.285321
  3. nVidia, 'Technical briefs: NVIDIA lights peed memory architecture II,' nVidia Corporation, available at http://www.nvidia.com/docs/lo/1452/SUPP/LMAII.2.02.pdf
  4. Tulika Mitra and Tzi-cker Chiueh, 'Dynamic 3d graphics workload characterization and the architecturaJ implications,' 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 62-71, Nov. 1999 https://doi.org/10.1109/MICRO.1999.809444
  5. W. C. Park, K. W. Lee, I. S. Kim, T. D. Han, and S. B. Yang, 'An effective pixel rasterization pipeline architecture for 3d rendering processors,' IEEE Transactions on Computers, accepted to appear, available at http://msl.yonsei.ac.kr/userweb/chan/thesis/TC114724.pdf https://doi.org/10.1109/TC.2003.1244948
  6. G. Lawton, 'The wild world of 3D graphics chips:' IEEE Computer, vol. 33, no. 9, pp.12-16, Sept. 2000 https://doi.org/10.1109/MC.2000.868692
  7. M. Woo, J. Neider, T. Davis, and D. Shreiner, OpenGL programming guide, Addison-Wesley, Third edition, 1999
  8. M. Deering, S.A.Schlapp, and M.G.Lavelle, 'Fbram : A new form of memory optimized for 3d graphics,' In Proceeddings of SIGGRAPH 1994, pp.167-174, July 1994 https://doi.org/10.1145/192161.192194
  9. M. D. Hill, J. R. Larus, A. R. Lebeck, M. Talluri, and D. A. Wood, 'Wisconsin architectural research tool set,' ACM SIGARCH Computer Architecture News, vol. 21, pp. 8-10, Sep. 1993 https://doi.org/10.1145/165496.165500
  10. ATI, 'Stunning 2d & 3d performance,' ATI Technologies INC., available at http://www.ati.com/technology/hardware/rage128pro/index.html
  11. ATI, '$RADEON^{TM}$ 8500LE : specification,' ATI Technologies INC., available at http://www.ati.com/products/pc/radeon8500Ie/specs.html
  12. http://www.idsoftware.com/games/quake/quake3-arena/
  13. http://www.spec.org/gpc/opc.static/opcview70.html