• Journal of Korea Multimedia Society
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• v.7 no.11
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• pp.1521-1530
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• 2004

In this paper, we present effective quantization noise reduction algorithm using signal adaptive filter and linear combination between blocks in multimedia system. In the proposed method, all of the blocks are classified into low frequency blocks, high frequency blocks, and midrange blocks according to DCT coefficients. Ringing artifacts are shown in high frequency blocks. So ringing artifact reduction algorithm is performed in high frequency blocks using a signal adaptive filter. And the blocking artifact reduction is performed by replacing the pixel value of blocky blocks using linear combination between blocky block and remote unblocky block. The simulation results shows better performance in respective of the subjective and objective image quality than the conventional method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.127-128
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• 2010

H.264/AVC는 부호화 효율을 높이기 위해 다양한 모드를 사용한다. 이런 다양한 모드들은 모두 부호화를 해봐서 발생하는 비용이 계산한다. 발생하는 비용은 영상의 화질과 비트로 구성되어 있으며, 영상의 화질이 좋고 발생비트가 가장 적은 모드가 선택 되어 복호기에 전송된다. 하지만 영상의 화질을 계산할 때 디-블록킹 필터의 효과를 무시해서 계산하기 때문에 정확한 모드를 선택하지 못하게 된다. 따라서 본 논문에서는 모드 결정시 디-블록킹 필터를 적용하여 정확한 영상의 화질을 계산하여 모드를 결정하는 방법을 제안한다. 그 결과 평균 1.021%의 BD-Rate를 감소시켰다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.117-118
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• 2013

본 논문에서는 HEVC (High Efficiency Video Coding) SAO (Sample Adaptive Offset)의 병렬화 성능을 비교한다. HEVC 의 참조 소프트웨어인 HM-10.0 에서는 SAO 수행 과정의 연산량 및 메모리 접근을 최소화하고 카테고리 계산 과정에서 SAO 수행 전의 픽셀값을 사용하기 위해서 라인 버퍼를 사용한다. 그러나 이러한 라인버퍼의 사용은 SAO 에 대해 데이터-레벨의 병렬화를 적용하기 어렵게 만드는 주요 요인이다. 본 논문에서는 HEVC 디블록킹 필터가 적용된 픽쳐를 추가 메모리에 복사하는 구현 방식과 HM-10.0 의 SAO 구현 방식 각각에 대해 데이터-레벨 병렬화를 적용하고 각각의 성능을 비교 분석하였다. 실험 결과, HEVC 디블록킹 필터가 적용된 픽쳐를 추가 메모리에 복사하는 구현 방식은 데이터-레벨 병렬화의 구현은 쉽지만, 디블록킹 필터링 된 픽쳐를 추가 메모리에 복사하는 부분 때문에 HM-10.0 기반의 병렬화보다 복호화 성능이 저하될 수 있음을 확인하였다. 이에 반해 CTU 의 행 단위로 병렬 수행될 영역을 분할하는 방식은 구현의 용이성과 병렬화 성능을 동시에 얻을 수 있음을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.562-564
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• 2004

캐시 선인출 기법은 메모리 참조에 따른 지연시간을 줄이는 효과적인 방법이다. 그러나 너무 적극적인 선인출은 캐시 오염을 유발시켜 선인출에 의한 장점을 상쇄시킨다. 본 연구에서는 캐시의 오염을 줄이기 위해 동적으로 필터 테이블을 참조하여 선인출 명령을 수행할 지의 여부를 결정하는 4가지 필터링 방법들을 비교 평가한다. 비교 연구를 위한 이상적인 필터링 구조를 제안하였으며, 기존 연구에서의 잠김 현상을 개선하기 위한 이진 상태 구조를 제안하였다. 또한, 정교한 필터링을 위한 블록주소 참조 방식을 제안하였다. 일반적으로 많이 사용되는 일반 벤치마크 프로그램과 멀티미디어 벤치마크 프로그램들에 대하여 실험한 결과, 캐시 미스율이 이진 상태 구조는 평균 5.6%, 블록주소 참조 구조는 7.9% 각각 감소하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.10
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• pp.700-707
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• 2014

In this paper, we propose the noise reduction method by using the eigenfilter in cyclic prefix system based on SNR. To obtain the signal eigenvectors for the eigenfiltering, we propose a method of obtaining the autocorrelation matrix by exploiting the circulant property of the received block which results from the cyclic extension of the OFDM symbol. Since the structures of the transmitter and the receiver are not changed, the proposed method is easy to apply to the conventional OFDM system. To verify the proposed method, we evaluate the persistency of excitation (POE) criterion for the input and demonstrate the effectiveness of the proposed method in the simulation results.

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.313-320
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• 2017

The In-loop filtering methods such as de-blocking filter and SAO(Sample Adaptive Offset) applied to the HEVC standard achieves coding efficiency and subjective quality improvement by reducing the blocking artifacts and the ringing artifacts. However, despite the use of In-loop filtering methods, the artifacts called a corner outlier occurring at the corner points of block boundaries are not removed. In this paper, the corner outlier artifacts are reduced by the detection, determination, and filtering processes on the corner outlier pixels. Experimental results show that the proposed method improves the subjective picture quality and slightly increases the coding efficiency in Inter prediction.

• Journal of Korea Multimedia Society
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• v.16 no.6
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• pp.756-763
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• 2013

Bilateral filter (BF), functioning by two Gaussian filters, domain and range filter is a nonlinear filter for sharpness enhancement and noise removal. In infrared (IR) small target detection field, the BF is designed by background predictor for predicting background not including small target. For this, the standard deviations of the two Gaussian filters need to be changed adaptively in background and target region of an infrared image. In this paper, the proposed bilateral filter make the standard deviations changed adaptively, using variance feature of mean values of surrounding block neighboring local filter window. And, in case the variance of mean values for surrounding blocks is low for any processed pixel, the pixel is classified to flat background and target region for enhancing background prediction. On the other hand, any pixel with high variance for surrounding blocks is classified to edge region. Small target can be detected by subtracting predicted background from original image. In experimental results, we confirmed that the proposed bilateral filter has superior target detection rate, compared with existing methods.