• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.291-297
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• 2004

In this paper, a new structure for the AEC(Acoustic Echo Canceller) is proposed in which echo signal components that can be created in mobile communications is effectively eliminated. Block Data Flow Architecture is a parallel architecture that achieves high performance, high efficiency, high throughput, and almost linear speed up. The proposed architecture employs AEC and is implemented using the TMS320C6711 for real-time applications. The proposed AEC shows improved performance by eliminating echoes at 55ms delay path. Since the proposed AEC can also be implemented in Firmware, it is believed to effectively work on various types of echoes if it is applied on CDMA mobile devices. The TMS320C6711 shows much better performance comparing to previous DSPs. For experimental verifications, filtering operation using adaptive algorithm is performed on TMS320C6711 board and error signals resulted from computations are monitored on PC, and then the performance of the implemented AEC is verified through ERLE computation. According the results of simulation, good characteristic of 100dB are shown after 500 sampling data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.63-70
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• 2015

In this paper, a receiver has been developed in a $0.11-{\mu}m$ CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as $5{\mu}W$. The chip size is $325{\mu}m{\times}290{\mu}m$ excluding the probing pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

• Journal of Korea Water Resources Association
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• v.46 no.10
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• pp.969-976
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• 2013

Leakage in water distribution system causes social and economic losses by direct water loss into the ground, and additional energy demand for water supply. This research suggests a leak detection model of using adaptive Kalman filtering on real-time data of pipe flow. The proposed model takes into account hourly and daily variations of water demand. In addition, the model's prediction accuracy is improved by automatically calibrating the covariance of noise through innovation sequence. The adaptive Kalman filtering shows more accurate result than the existing Kalman method for virtual sine flow data. Then, the model is applied to data from two real district metered area in JE city. It is expected that the proposed model can be an effective tool for operating water supply system through detecting burst leakage and abnormal water usage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.917-922
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• 2010

In this paper, a new temperature-insensitive CMOS dual-mode current reference for low-voltage low-power mixed-mode circuits is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature(PTAT) current and a complementary to absolute temperature(CTAT) current. The temperature insensitivity was achieved by the mobility and the other which is inversely proportional to mobility. As the results, the temperature dependency of output currents was measured to be $0.38{\mu}A/^{\circ}C$ and $0.39{\mu}A/^{\circ}C$, respectively. And also, the power dissipation is 0.84mW on 2V voltage supply. These results are verified by the $0.18{\mu}m$ n-well CMOS parameter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.4
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• pp.19-28
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• 2009

This paper is a study on method that the EZW algorithm is proposed effective compression technique of wavelet transformed image. The EZW algorithm is encoded by zerotree coding technique using self-similarity of wavelet coefficients. If the coefficient is larger than the threshold a POS coded, if the coefficients is smaller than minus the threshold a NEG is coded. If the coefficient is the root of a zerotree than a ZTR is coded and finally, if the coefficient is smaller then the threshold but it is not the root of a zerotree, than an IZ is coded. This process is repeated until all the wavelet coefficients have been encoded completely. This paper was compared to EZW algorithm and a widely available version of JPEG. As the results of compare, it is shown that the PSNR of the EZW algorithm is better than JPEG.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.286-296
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• 2005

This paper presents a stereo-based image compression and transmission system for 3D realistic television. In the proposed system, a disparity map is extracted from an input stereo image pair and the extracted disparity map and one of two input images are transmitted or stored at a local or remote site. However, correspondences can not be determined in occlusion areas. Thus, it is not easy to recover 3D information in such regions. In this paper, a reconstruction image compensation algorithm based on error block concealment and in-loop filtering is proposed to minimize the reconstruction error in generating stereo image pair. The effectiveness of the proposed algorithm is shown in term of objective accuracy of reconstruction image with several real stereo image pairs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.313-315
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• 2010

In this paper, we describe research results of developing hardware rasterizer that is applicable to mobile 3D graphics system, designed in SIMD architecture and verified in FPGA. Tile-based scan conversion unit is designed like SIMD architecture running four tiles simultaneously and each tile traverses pixels hierarchical in 3-level so that visiting counts is minimized. As experimental results, $8{\times}8$ is the most efficient size of tile and the last step of tile traversing is performed on $2{\times}2$ sized subtile. The rasterizer supports flat shading and gouraud shading and texture mapper supports affine mapping and perspective corrected mapping. Also, texture mapper supports point sampling mode and bilinear interpolating sampling mode and two types of wrapping modes and various blending modes. The rasterzer operates as 120Mhz on xilinx vertex4 $l{\times}100$ device. To easy verification, texture memory and frame buffer are generated as block rom and block ram.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.5
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• pp.339-345
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• 2016

In general, mosaic blocks are used to hide some specified areas, such as human faces and disgusting objects, in an input image when images are uploaded on a web-site or blog. This paper proposes a new algorithm for robustly detecting grid mosaic areas in an image based on the edge projection. The proposed algorithm first extracts the Canny edges from an input image. The algorithm then detects the candidate mosaic blocks based on horizontal and vertical edge projection. Subsequently, the algorithm obtains real mosaic areas from the candidate areas by eliminating the non-mosaic candidate regions through geometric features, such as size and compactness. The experimental results showed that the suggested algorithm detects mosaic areas in images more accurately than other existing methods. The suggested mosaic detection approach is expected to be utilized usefully in a variety of multimedia-related real application areas.