• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3160-3162
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• 2000

변화 부호화는 기존에 부호화 되어있는 영상의 비트율을 더 낮은 비트율의 영상으로 재 부호화하거나. 다른 부호화 표준으로 재 부호화 하는 기법이다. 변환 부호화기의 설계에서 가장 중요시되는 문제는 화질 향상과 부호화 속도의 향상이다. 변환 부호화기의 많은 응용분야에서 실시간 변환을 필요로 하기 때문에 변환 속도를 향상시키면서 화질을 높이는 방법이 연구되어 왔다. 비트율 변환비가 매우 클 때에나 표준화 방법의 목적 영상 사이즈가 다를 때엔 비트율의 변환과 함께 영상의 크기를 함께 변환(1/2)해 주어야할 필요가 있다. 본 논문에서는 이러한 경우에 적합한 변환 부호화기법을 제안한다. 우선 영상의 크기를 다운스케일링 해 준후, 기존 영상의 움직임 벡터들로부터 AWW기법을 이용해 1차 추정 벡터를 추출하여 속도를 향상시키고, 1차 추출 벡터 부근의 한정된 영역으로부터 움직임 벡터 추정과정을 거쳐 최종 추정 벡터를 정제하여 화질을 향상시킨다. 실험 결과 기존의 재 부호화 기법에 비해 속도가 향상됨을 확인 할 수 있었으며. AWW 기법에 비해 연산량은 조금 많아지나 정제 과정을 통하여 약 1dB 정도의 화질 향상이 있음을 확인할 수 있었다.

• Proceedings of the Korea Society for Simulation Conference
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• 1999.04a
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• pp.53-53
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• 1999

제품에 대한 수요의 다양화에 대응하기 위해서, 다품종소량생산방식이 정착하고 있다. 다품종소량생산을 효율적으로 실현하는 현대의 전형적인 자동화생산시스템으로서, 유연생산시스템(Flexible Manufacturing System : 이하 FMS)이 급속히 보급되어, FMS의 효율적인 운영이 생산현장에 있어서 중요한 과제가 되고 있다. 다수의 품종이 동시에 병행해서 반복적으로 생산되는 실제의 FMS에서는, 품종의 생산에 필요한 일련의 작업의 종류에 대한 우선순서인 "투입우선순서(Dispatching Priority)"를 설정해서, 그것을 기반으로 시스템이 운영되는 것이 보통이다.본 연구에서는 투입우선순서로 제어되는 동일한 품종의 반복이 있는 FMS를 염두에 두고, 생산요건이 확정적인 상태에서 주어진 평가척도를 최적화하는 투입우선순서를 결정하는 문제로써, FMS의 투입우선순서 결정문제 (FMS dispatching priority problem)를 제기하여, 시뮬레이션을 통해서 그 해법을 논한다. 실재하는 많은 FMS에 있어서 투입우선순서를 단기간에 용이하게 정할 수 있는 우선규칙(dispatching rule)이 실용적으로 넓게 이용되고 있다. 종래로부터, ？샵(job shop)을 대상으로 하는 다수의 우선규칙이 제안, 평가되어 왔지만, 그것들은 각 품종이 서로 다른 종류의 일감인 것을 상정하고 있으며, 동일한 품종의 일감의 존재를 의식하고 있지 않다. 본 연구에서는 재래형의 ？샵 환경에 있어서 그 유효성이 검증되어 있는 기존의 표준적인 우선규칙의 성능이, 동일한 품종의 반복이 있는 경우에도 잘 기능하는지 어떤지를 시뮬레이션을 통해 평가한 후에, 오더사이즈(order size)를 고려한 우선규칙을 제안하고, 납기지체의 평가척도에 관한 유효성을 명확히 하고 있다. 시뮬레이션 실험의 결과에서는, 우선규칙의 기본적인 결정요인이 성능에 미치는 영향을 통계적으로 분석하고 있다.로 분석하고 있다.

• Journal of Korean Society of societal Security
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• v.4 no.1
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• pp.49-55
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• 2011

The primary objective of this paper is to develop optimal algorithms of reinforced concrete frame structural systems by the limit state design(CP 1110) and to look into the possibility of detailed design of these structural systems. The structural formulation is derived on the finite element method. The objective of optimization of a reinforced structure for a specified geometry is mainly to determine the optimum cross-sectional dimensions of concrete and the area of the various sizes of the reinforcement required for each member. In addition to the detail s such as the amount of web reinforcement, cutoff points of longitudinal reinforcedments etc. are also considered as design variables. In this study, the method of "Generalized Reduced Gradient, Rounding and with Neighborhood search" and "the Sequential Linear Programming" are employed as an analytical method of nonlinear optimization.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.35-43
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• 2003

The randomization of scalar multiplication in ECC is one of the fundamental concepts in defense methods against side-channel attacks. This paper proposes a countermeasure against simple and differential power analysis attacks through randomizing the transformed m-ary method based on a random m-ary receding algorithm. The proposed method requires an additional computational load compared to the standard m-ary method, yet the power consumption is independent of the secret key. Accordingly, since computational tracks using random window width can resist against SPA and DPA, the proposed countermeasure can improve the security for smart cards.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2783-2790
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.141-146
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• 2016

HEVC/H.265 is the latest joint video coding standard proposed by ITU-T SG 16 WP and ISO/IEC JTC 1/SC29/WG 11. In H.265, pictures are divided into a sequence of coding tree units(CTUs), and the CTU further is partitioned into multiple CUs to adapt to various local characteristics. Its coding efficiency is approximately two times high compared to previous standard H.264/AVC. However according to the size of extended CU(coding unit) and transform block, the hardware size of PMR(prediction/mode decision/reconstruction) block within video encoder is about 4 times larger than previous standard. In this study, we propose a new less complex hardware architecture of PMR block which has the most high complexity within encoder without any noticeable PSNR loss. Using this simplified block, we can shrink the overall size the H.265 encoder. For FHD image, it operates at clocking frequency of 300 MHz and frame rate of 60 fps. And also for the test image, the Bjøntegaard Delta (BD) bit rate increase about average 30 % in PMR prediction block, and the total estimated gate count of PMR block is around 1.8 M.

• Journal of the Korean Society of Clothing and Textiles
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• v.32 no.6
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• pp.999-1011
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• 2008

To most of the students studying fashion related major, the graduation fashion show is a big challenge. They have to put together all they learn and show what they can do to their future employers. They design, pattern work, and make up garments for the show all by themselves. Unfortunately. while they make up their garments, they usually don't Dow exactly body measurements of the models. So quite often they have to alter their art works up to the last minute of the fashion show opening. Sometimes such unadequate work process ruins their work. The purpose of this study is to suggest block patterns of Korean fashion models measurements for basic items, such as jacket and pants for male models and torso length block pattern, skirt and pants for female models. 20 male and 20 female professional models were measured. The block patterns were based on their measurements. After the first fitting test, patterns were corrected by their body characteristic. For both male and female models, it was found desirable to fix the shoulder width and make an adjustment to the patterns with a deviation of width and girth items. In case of the resultant patterns the satisfaction was made better. Model sizes proposed in this study are considered closer to the size of average models, since they were based on A-grade models who are currently working in Korea. The resultant patterns can be produced by simply making a slight adjustment to the width of the proposed pattern in this study.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.7
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• pp.4588-4594
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• 2014

In this study, small scaled (1/30) laboratory chamber tests of the pile foundation for a lightweight concrete pavement system were carried out to evaluate the safety of a pile foundation on sandy soil. The testing ground was simulated in the field and a standard pile-loading test was conducted. The test piles were divided into 3 types, Cases A, B and C, which is the location from the center of the slab by applying a vertical load. The interval between the piles was set to 8 cm. As a result of the pile foundation model test, the pavement settled when the vertical load was increased to 12kg from 1.5kg in sandy soil ground, particularly the maximum settlement of 0.04mm. Judging from the model chamber test, Case A showed compressive deformation, whereas Case B represented the compression and tensile forces with increasing vertical load. Case C showed an increase in tensile strain.

• Journal of IKEEE
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• v.20 no.2
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• pp.192-195
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• 2016

In this paper, we present a nanopower CMOS bandgap voltage reference working in sub-threshold region without resisters and bipolar junction transistors (BJT). Complimentary to absolute temperature (CTAT) voltage generator was realized by using two n-MOSFET pair with body bias circuit to make a sufficient amount of CTAT voltage. Proportional to absolute temperature (PTAT) voltage was generated from differential amplifier by using different aspect ratio of input MOSFET pair. The proposed circuits eliminate the use of resisters and BJTs for the operation in a sub-1V low supply voltage and for small die area. The circuits are implemented in 0.18um standard CMOS process. The simulation results show that the proposed sub-BGR generates a reference voltage of 290mV, obtaining temperature coefficient of 92 ppm/$^{\circ}C$ in -20 to $120^{\circ}C$ temperature range. The circuits consume 15.7nW at 0.63V supply.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.245-252
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• 2008

In this paper, we propose a new method for improving the H 264 encoding process and motion estimation part. Our approach is a method to reduce the encoding running time through the omission of reference frame in the mode selection process of H 264 and an improvement of SAD computing process. To evaluate the proposed method, we used the H 264 standard image of QCIF size and TIN 4:2:0 format. Experimental results show that proposed SAD algorithm 1 can improve the speed of encoding runnung time by an average of 4.7% with a negligible degradation of PSNR. However, SAD algorithm 2 can improve the speed of encoding runnung time by an average of 9.6% with 0.98dB degradation of PSNR.