• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.50-50
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• 2007

최근 DRAM 소자 내에서 Ruthenium (Ru) 은 높은 화학적 안정성, 누설전류에 대한 높은 저항성, 고유전체와의 높은 안정성등과 같은 특성으로 인해 금속층-유전막(insulator)-금속층 캐패시터에 대한 하부전극으로 각광받고 있다. 일반적으로 Ru은 화학적으로 매우 안정하여 습식 식각으로 제거하기 어려우며, 이로인해 건식 식각을 이용하여 Ru을 제거하는 것이 널리 통용되고 있다. 하지만 칵 캐패시터의 분리를 위해 Ru을 건식 식각할 경우, 유독한 $Ru0_4$ 가스가 발생할 수 있으며 Ru 하부전극의 탈균일한 표면과 몰드 산화막의 손실을 유발할 수 있다. 이로인해 각 캐패시터간의 분리와 평탄화를 위해 CMP 공정이 도입되게 되었다. 이러한 CMP 공정에 공급되는 슬러리에는 부식액, pH 적정제, 연마입자등이 첨가되는데 이때 연마입자가 응집하여 슬러리의 분산 안정성 저하에 영향을 줄 수 있다. 그리하여 본 연구에서는 Ru CMP Slurry에서의 surfactant와 같은 첨가제에 따른 zeta potential, particle size, sedimentation의 분석을 통해 slurry 안정성에 대란 영향을 살펴보았다. 또한 선택된 surfactant가 첨가된 Ru CMP Slurry를 제조하여 Ru의 removal rate와 TEOS에 대한 selectivity를 측정해 보았다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.81-81
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• 2007

Chemical mechanical polishing (CMP) 공정은 deep 서브마이크론 집적회로의 다층배선구조률 실현하기 위해 inter-metal dielectric (IMD), inter-layer dielectric layers (ILD), pre-metal dielectric (PMD) 층과 같은 절연막 외에도 W, Al, Cu와 같은 금속층을 평탄화 하는데 효과적으로 사용되고 있으며, 다양한 소자 제작 및 새로운 물질 등에도 광범위하게 응용되고 있다. 하지만 Cu damascene 구조 제작으로 인한 CMP 응용 과정에서, 기계적으로 깨지기 쉬운 65 nm의 소자 이하의 구조에서 새로운 저유전상수인 low-k 물질의 도입으로 인해 낮은 하력의 기계적 연마가 필요하게 되었다. 본 논문에서는 전기화학적 기계적 연마 적용을 위해, I-V 특성 곡선을 이용하여 active, passive, transient, trans-passive 영역의 전기화학적 특성을 알아보았으며, Cu 막의 표면 형상을 알아보기 위해 scanning electron microscopy (SEM) 측정과 energy dispersive spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• Transactions on Semiconductor Engineering
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• v.2 no.2
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• pp.1-9
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• 2024

CMP (Chemical Mechanical Polishing) processes have become essential for creating multilayered component structures in semiconductor manufacturing. Typically, the slurry composition in CMP processes involves a balance of three components such as ceria, dispersant, and deionized water. In this study, we conducted research on the stability of ceria slurries using an amphoteric surfactant with controlled concentrations of AMP (2-Amino-2-methyl-1-propanol). The results indicated pH stabilization influenced by carboxylic (-COOH) groups depending on the AMP concentration. Additionally, there was no occurrence of aggregation in the ceria slurry, confirming the absence of dispersion stability issues.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.17-23
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• 2002

The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18 $\mu\textrm{m}$ semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.61-66
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• 2012

Chemical Mechanical Planarization (CMP) is a polishing process used in the microelectronic fabrication industries to achieve a globally planar wafer surface for the manufacturing of integrated circuits. Pad conditioning plays an important role in the CMP process to maintain a material removal rate (MRR) and its uniformity. For metal CMP process, highly acidic slurry containing strong oxidizer is being used. It would affect the conditioner surface which normally made of metal such as Nickel and its alloy. If conditioner surface is corroded, diamonds on the conditioner surface would be fallen out from the surface. Because of this phenomenon, not only life time of conditioners is decreased, but also more scratches are generated. To protect the conditioners from corrosion, thin organic film deposition on the metal surface is suggested without requiring current conditioner manufacturing process. To prepare the anti-corrosion film on metal conditioner surface, vapor SAM (self-assembled monolayer) and FC (Fluorocarbon) -CVD (SRN-504, Sorona, Korea) films were prepared on both nickel and nickel alloy surfaces. Vapor SAM method was used for SAM deposition using both Dodecanethiol (DT) and Perfluoroctyltrichloro silane (FOTS). FC films were prepared in different thickness of 10 nm, 50 nm and 100 nm on conditioner surfaces. Electrochemical analysis such as potentiodynamic polarization and impedance, and contact angle measurements were carried out to evaluate the coating characteristics. Impedance data was analyzed by an electrical equivalent circuit model. The observed contact angle is higher than 90o after thin film deposition, which confirms that the coatings deposited on the surfaces are densely packed. The results of potentiodynamic polarization and the impedance show that modified surfaces have better performance than bare metal surfaces which could be applied to increase the life time and reliability of conditioner during W CMP.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.1-6
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• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.1
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• pp.51-56
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• 2018

To evaluate surface characteristics of AlN single crystal grown by physical vapor transport (PVT) method, chemical mechanical polishing (CMP) were performed with diamond slurry and $SiO_2$ slurry after mechanical polishing (MP), then the surface morphology and analysis of polishing characteristics of the slurry types were analyzed. To estimate how pH of slurry effects polishing process, pH of $SiO_2$ slurry was controlled, the results from estimating the effect of zeta potential and MRR (material removal rate) were compared in accordance with each pH via zeta potential analyzer. Eventually, surface roughness RMS (0.2 nm) could be derived with atomic force microscope (AFM).

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.774-779
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• 2013

We synthesized the solution processible monodispersed $TiO_2$ crystalline nano-sol with ~ 5 nm in size by sol-gel method. Through the spin-coating of crystalline $TiO_2$ nano-sol at low processing temperature, we could make even blocking interlayer on the rough FTO transparent electrode substrate. The rough FTO surface could be gradually smoothed by the spin-coating of nano-crystalline $TiO_2$ sol based blocking interlayer. The 1, 2.5, 5, and 10 wt% of nanocrystalline $TiO_2$ sol formed 29, 38, 62, and 226 nm-thick of blocking interlayer in present experimental condition, respectively. The 5 and 10 wt% of $TiO_2$ nano-sol could effectively fill up the valley part of bare FTO with 48.7 nm of rms (root mean square) roughness and consequently enabled the ZnO to be grown to vertically aligned one dimensional nanorods on the flattened blocking interlayer/FTO substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.125-125
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• 2010

극성 [0001] 방향으로 성장된 질화물 기반의 LED (light emitting diode) 는 분극현상에 의해 발생하는 강한 내부 전기장의 영향을 받게 된다. 이러한 내부 전기장은 양자우물 내의 전자와 정공의 공간적 분리를 야기하고 quantum confined Stark effect (QCSE)에 의한 발광 파장의 적색 편이가 발생하며 양자효율의 저하를 가져오게 된다. 이러한 문제를 해결하기 위해 InGaN/GaN이나 AlGaN/GaN 양자 우물구조를 GaN의 m-plane (1$\bar{1}$00) 이나 a-plane (11$\bar{2}$0) 등 비극성면 위에 성장하려는 시도를 하고 있다. 그러나 비극성 면의 비등방성 (anisotropy) 으로 인하여 결정성이 높은 비극성 GaN을 성장하는 데에는 많은 어려움이 있다. GaN 층의 표면을 평탄화하고 결정성을 향상시키기 위해서 저온 GaN 또는 AlN 버퍼층을 성장하는 2단계 방법이나 고온 버퍼층을 이용하여 성장하는 연구들이 많이 진행되고 있다. 본 연구에서는 고온 GaN 버퍼층을 이용하여 기존의 2단계 성장과정을 단순화한 비극성 a-plane GaN을 r-plane 사파이어 기판위에 유기금속 화학증착법 (MOCVD)으로 성장하였다. 사파이어 기판위에 AlN 층을 형성하기 위한 nitridation 과정 후 1030 도에서 두께 45 ~ 800 nm의 고온 GaN 버퍼층을 성장하고 총 박막 두께가 2.7 ~ 3 um 가 되도록 a-plane GaN을 성장하여 표면 양상의 변화와 결정성을 확인하였다. 또한 a-plane GaN 박막 성장 시에 성장 압력을 100 ~ 300 torr 로 조절하며 박막 성장의 변화 양상을 관찰하였다. 고온 GaN 버퍼층 성장 두께가 감소함에 따라 결정성은 증가하였으나 표면의 삼각형 형태의 pit 밀도가 증가함을 확인하였다. 또한 성장 압력이 감소함에 따라 표면 pit은 감소하였으나 결정성도 감소하는 것을 확인하였다. 성장 압력과 버퍼층 성장 두께를 조절하여 표면에 삼각형 형태의 pit이 존재하지 않는 RMS roughness 0.99 nm, 관통전위밀도 $1.78\;{\times}\;10^{10}/cm^2$, XRD 반가폭이 [0001], [1$\bar{1}$00] 방향으로 각 798, 1909 arcsec 인 a-plane GaN을 성장하였다. 이 연구를 통해 고온 GaN 버퍼 성장방법을 이용하여 간소화된 공정으로 LED 소자 제작에 사용할 수 있는 결정성 높은 a-plane GaN을 성장할 수 있는 가능성을 확인하였다.