• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.295-297
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• 1998

인터넷 상에서 AOD나 VOD와 같이 멀티미디어 데이터를 서비tm하는 시스템에서는 같은 자원으로 더 많은 수의 동시 사용자를 지원하는 문제가 중요하다. 기존의 운영체제 캐쉬만을 이용하면 자주 요청되지 않는 곡에 대한 스캔으로 캐쉬에서 페이지 교체가 자주 일어나 버퍼링 효과가 저하되는 현상이 있다. 본 논문에서는 웹캐쉬라는 구조를 통해 과거의 요청 정보로부터 가까운 미래에 다시 요청될 곡들을 예측하고 이 곡들을 웹캐쉬에 유지하여 서비스한다. 이렇게 함으로써 디스크 액세스 횟수를 줄일 수 있고 같은 자원으로 더 많은 동시 사용자를 지원할 수 있다. 가까운 미래에 다시 요청될 곡을 예측하기 위한 방법으로 과거 요청 사이의 시간간격에 가중치를 부여하여 요청이 자주 발생하는 곡들을 판별해 낼 수 있다. 실제로 운영되고 있는 AOD 사이트의 4달간의 요청 자료를 실험 자료로 본 논문에서 주장하는 바를 시뮬레이션하여 높은 성능 향상을 얻은 것을 보였다.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.1
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• pp.1-13
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• 1999

웹의 등장은 인터넷 인구의 엄청난 성장을 가져왔다. 이와 더불어 최근에는 가상 금융 및 전자 상거래 시장등을 지원하는 웹 상의 데이터베이스 관련 상품들이 속속 등장하고 있다. 이에 기존의 데이터베이스 시스템과 클라이언트-서버 방식으로 동작하던 응용 프로그램들은 웹 환경에 적합한 상호 연동방식을 요구한다. 본 논문에서는 관계형 DBMS인 SRP를 웹상에서 동작시키기 위한 통로인 SWeS를 제시한다. SWes는 CGI를 이용한 응용서버 방식으로 구현하였으며, 동적 서버 교체와 페이지 단위의 결과 전송 기법등을 사용해 가용성 및 동시성,확장성을 높이는 구조를 갖는다.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.412-421
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• 2009

Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, and therefore erase operations are required prior to rewriting. These extra operations cause performance degradation of NAND flash memory file system. Since it also has an upper limit to the number of erase operations for a specific location, frequent erases should reduce the lifetime of NAND flash memory. These problems can be resolved by delaying write operations in order to improve I/O performance: however, it will lower the cache hit ratio. This paper proposes a policy of page management using double cache for NAND flash memory file system. Double cache consists of Real cache and Ghost cache to analyze page reference patterns. This policy attempts to delay write operations in Ghost cache to maintain the hit ratio in Real cache. It can also improve write performance by reducing the search time for dirty pages, since Ghost cache consists of Dirty and Clean list. We find that the hit ratio and I/O performance of our policy are improved by 20.57% and 20.59% in average, respectively, when comparing them with the existing policies. The number of write operations is also reduced by 30.75% in average, compared with of the existing policies.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.445-458
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• 2007

This article presents a novel infrastructure for large-memory database processing using commodity hardware with operating system support. We exploit inexpensive PCs and a high-speed network capable of Remote Direct Memory Access (RDMA) operations to build a new memory hierarchy between fast volatile memory and slow disk storage. The new memory hierarchy guarantees a reasonable response time, and its storage size enables us to run large-memory database systems with little performance degradation. The proposed architecture has two main components: (1) a remote memory system inside the Linux kernel to manage other computers' memory pages efficiently and (2) a remote memory pager responsible for manipulating remote read/write operations on remote memory pages. We insist that the proposed architecture is practical enough to support the rigorous demands of commercial in-memory database systems by demonstrating the performance of publicly available main-memory databases (e.g., MySQL) on our prototyped system. The experimental results show very interesting results from the TPC-C benchmark.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.1
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• pp.134-139
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• 2022

Recently, interest in programming and artificial intelligence is continuously increasing, and software education is being implemented as a mandatory education from elementary school. For efficient programming education, it is basically necessary to build a lab environment suitable for students and teachers, but there are performance problems due to the inadequacy of old computers and network equipment. Therefore, in this paper, we propose a web page-based online practice environment and algorithm competition scoring system using React and Spring boot to solve the problem of the programming practice environment. Through this, it is thought that programming learning can be carried out using only a web browser even on low-spec computers. In addition, since various programming languages can be learned irrespective of the language to be learned, it is considered that the time cost for establishing a practice environment can be reduced.

• Annual Conference of KIPS
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• 2001.10b
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• pp.1383-1386
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• 2001

Internet 이용자의 급격한 증가와 광대역 통신망(B-ISDN) 구축의 확산에 따라 ATM(Asynchronous Transfer Mode)망 접속장치의 큰 수요가 기대되며, 또한 ATM망 접속장치의 성능 향상도 요구되고 있다. 기존의 연구들은 컴퓨터 프로그램의 메모리에 대한 참조가 지역적이라는 특성을 이용한 가상 메모리의 효율적인 페이지 교체 알고리즘 및 캐쉬 처리 방안들이 진행되어 왔다. 본 논문은 ATM 프로토콜 프로세서를 설계하는데 있어 네트워크 트래픽의 지역성(Locality of Reference)을 고려한 캐쉬 메모리 구조를 적용하여 보다 향상된 ATM 셀 수신이 가능하도록 한다. ATM 셀의 가상 패스 식별자/가상 채널 식별자(VPI/VCI)를 캐쉬 처리함으로써, 패킷을 분해, 재조립(Segmentation and Reassembly)할 때 관련 테이블의 검색 시간을 줄일 수 있다. 캐쉬 메모리 적용으로 인한 성능 향상을 평가하기 위해 ATM NIC 프로세서와 내부 캐시 메모리 그리고, 외부 SRAM 사이에 셀 수신 정보의 Read 와 Write에 드는 시간 비용(System Clock Cycle)을 캐시의 Hit 또는 Miss 등에 따라 구분하고, 이를 기반으로 한 시뮬레이터에 3 종류의 ATM 셀 스트림을 가하여 각각에 대해 평균 셀 처리시간, 데이터 버스의 트래픽 비율 그리고, 히트율의 3가지 평가요소를 측정하고, 비교하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1476-1484
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• 1999

TV 방송 분야에서 다양한 정보와 상호 작용성을 제공하기 위해서 최근 기존 방송 내용인 A/V 스트림 외 부가정보 방송이 시도되고 있다. 데이타 방송에 대한 기존 연구는 대부분 고정된 내용의 데이타를 방송하는 환경을 가정하고 있어서 그 결과가 방송 내용의 변화가 많은 환경에 부적합하다. 본 논문에서는 데이타에 대한 접근이 반복되지 않을 가능성이 높고 사용자 접근 확률을 예상하기 어려운 상황에서 응답 시간을 개선하는 방안으로 수신 데이타를 무조건 캐쉬에 반입하고 교체가 필요한 경우 다음 방송 시각이 가장 가까운 페이지를 축출하는 사용자 단말 시스템에서의 캐슁 정책을 제안하였다. 제안된 캐쉬 관리 정책은 평균적인 캐쉬 접근 실패 비용을 줄임으로써 사용자 응답 시간을 개선하며, 서로 다른 스케줄링 기법을 사용하는 다양한 방송 제공자가 공존하는 환경에서 보편적으로 효과를 가져올 수 있다.Abstract Recently, many television broadcasters have tried to disseminate digital multimedia data in addition to the traditional content (audio-visual stream). The broadcast data need to be cached by a client system, to provide a reasonable response time for a user request. Previous studies assumed the dissemination of a fixed set of items, and the results are not suitable when broadcast items are frequently changed. In this paper, we propose a novel cache management scheme that chooses the replacement victim based on the remaining time to the next broadcast instance. The proposed scheme reduces response time, where it is hard to predict the probability distribution of user accesses. The caching policy we present here significantly reduces expected response time by minimizing expected cache miss penalty, and can be applied without difficulty to different scheduling algorithms.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1375-1385
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• 1996

As there has been much demands for processing multimedia data, a storage manager for multimedia data makes much effects on system performance. Because the size of multimedia data is usually very large, disk I/O for the data consumes much time and causes the system performance to be decreased. Therefore, it makes a better effect on system performance that a multimedia data storage manager decreases its disk I/O by the buffer management of multimedia data. This paper proposes a buffer management technique which allocates the buffer to be equal to its corresponding segment which consists of physically continuous disk page set and is disk management unit for multimedia data in many multimedia data storage manager. As the size of buffer varies, it also proposes a buffer replacement policy which consider not only reference behavior of buffer but also buffer size The proposed multimedia data buffer management technique is implemented in KORED/STORM which is a storage manager for multimedia data.