• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.7
• /
• pp.970-979
• /
• 1993

In this paper, a multi-function processor unit is implemented for binary image processing. This unit consists of a set of address generatior, window pipeline register, look up table, control unit, and two local memories .The merits of multi-function processor unit are more simpler than basic SAP and improved disposal speed. A simple software selection give the various choices of image sizes and it can process the function of smoothing, thinning, feature extraction, and edge detection, selectively or sequentially.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.3B
• /
• pp.362-368
• /
• 2001

본 논문에서는 두 개의 17비트 오퍼랜드를 radix-4 Booths 알고리즘을 이용하여 곱셈 연산을 수행하는 곱셈기를 설계하고 효율적인 풀커스팀 디자인에 대한 테스트 방법을 제안하였다. 클럭 속도를 빠르게 하기 위하여 2단파이프라인 구조로 설계하고 규칙적인 레이아웃을 위해 4:2 CSA(Carry Save Adder)를 사용하였다. 회로는 LG 반도체의 0.6-um 3-Metal N-well CMOS 공정을 사용하여 칩으로 제작되었다. 새로운 개념의 모듈레벨 고착 고장 모델을 제안하였고 제안한 테스트 방법을 사용하여 관찰해야 하는 노드의 수를 약 88% 줄여 효율적인 고장 시뮬레이션을 수행하였다. 설계된 곱셈기는 9115개의 트랜지스터로 구성되며 코어 부분의 레이아웃 면적은 약 1135*1545 um2 이다. 제작된 칩은 전원접압 5V에서 약 24MHz의 클럭 주파수로 동작한다.

• Journal of the KSME
• /
• v.30 no.2
• /
• pp.146-154
• /
• 1990

수냉형의 Bo kg/$\textrm{mm}^2$1급 TMCP 고장력 강재를 중심으로, 이 강재 모재의 기계적 특성 및 용접부의 각종 사용특성에 관해 종래의 압연제법에 의한 동일강도레벨의 고장력강판과 비교하여 고찰하고 이 강재의 유효이용에 대하여 설명하였다. TMCP 고장력 강판은 탄소당량이 낮고 결 정립 미세화가 달성되기 때문에 파괴인성이나, 용접부의 내외화, 내용접균열성 면에서 탁월한 특 징을 가지나 용접조립시 용접열사이클로 인한 연화현상 때문에 용접부의 사용특성이 문제로 될 수 있다. 그러나 용접조건이나, 강판의 강도, 화학성분의 배려, 선택에 따라 실용상 별로 문제가 되지 않음이 확인하고 있다. 이와 같은 특징으로 인해 TMCP강은 조선용 소재뿐만 아니고, 북해, 북극해와 같은 한냉빙해역의 가혹한 환경에서 작동되는 해양구조물용이나 라인 파이프용 소재 로서도 그 활용이 확대되어 갈 것으로 생각된다.

• Journal of Institute of Control, Robotics and Systems
• /
• v.4 no.3
• /
• pp.329-333
• /
• 1998

본 논문에서는, LSI 적층 기술을 이용한 실시간 처리 마이크로 비젼의 개발을 소개하고 있다. 새롭게 개발된 LSI 적층기술을 이용하여, 영상신호의 증폭, 변환, 연산처리등의 기본기능을 가지는 다수의 LSI 웨이퍼를 적층한다. 각 층간의 고밀도 수직배선을 통하여 대량의 영상정보를 동시에 전달하므로써, 대규모 동시 병렬처리를 가능하게 하며, 다수의 층에 걸쳐 파이프 라인 처리가 이루어진다. VLSI 설계시스템을 이용하여, 윤곽 검출기능을 가지는 테스트 칩을 설계(2 .mu.m CMOS design rule)하고, 시뮬레이션을 통하여 양호한 동작(처리시간 10 .mu.s)을 확인하고 있다. 시험제작을 위해서는, 새롭게 개발된 LSI 적층기술이 이용된다. 영상처리의 기본회로가 실려있는 웨이퍼의 기반을 30 .mu.m 의 두께까지 연마하고, 개발된 웨이퍼 aligner를 이용하여 수직배선이 형성된 상하 두 개의 웨이퍼를 미세조정하면서 접착한다. 이상의 제작과정을 반복하여 두께 1mm이하의 인공망막과 같은 마이크로 비젼을 제작한다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.53-60
• /
• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3235-3245
• /
• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.4C
• /
• pp.365-373
• /
• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.295-298
• /
• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.25-33
• /
• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Korean Society for Marine Environment & Energy
• /
• v.15 no.2
• /
• pp.67-75
• /
• 2012

Carbon-dioxide capture and storage (CCS) process is consisted by capturing carbon-dioxide from large point source such as power plant and steel works, transporting and sequestrating captured $CO_2$ in a stable geological structure. During CCS process, it is inevitable of introducing impurities from combustion, capture and purification process into $CO_2$ stream. Impurities such as $SO_2$, $H_2O$, CO, $N_2$, Ar, $O_2$, $H_2$, can influence on process efficiency, capital expenditure, operation expense of CCS process. In this study, experimental apparatus is built to simulate the behavior of $CO_2$ transport under various impurity composition and process pressure condition. With this apparatus, $N_2$ impurity effect on $CO_2$ mixture transportation was experimentally evaluated. The result showed that as $N_2$ ratio increased pressure drop per mass flow and specific volume of $CO_2-N_2$ mixture also increased. In 120 and 100 bar condition the mixture was in single phase supercritical condition, and as $N_2$ ratio increased gradient of specific volume change and pressure drop per mass flow did not change largely compared to low pressure condition. In 70 bar condition the mixture phase changed from single phase liquid to single phase vapor through liquid-vapor two phase region, and it showed that the gradient of specific volume change and pressure drop per mass flow varied in each phase.