• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.105-113
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• 2004

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.765-768
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• 2012

Recently, the supply ratio of smart devices application has become increasable, utilization of device increases constantly. At the same time, used application is more gentrified. However, using time of devices is decreased. To solve these problems, many research is studying about the hardware/software. One of them is profiling power consumption by process units. The process can be managed, based on measured energy consumption data. These means that it can efficiently use the residual energy. Application at the stage of program design can analyze and used-energy using the trace by considering the low-power can design. In this paper, we studied software-based power-metering framework for android platform. We survey each process-level power consumption measurement techniques, compare advantages and disadvantages of the technique and propose improved measures.

• Journal of the Korea Society of Computer and Information
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• v.25 no.4
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• pp.1-9
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• 2020

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.109-110
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• 2008

본 논문에서는 900MHz RFID 수동형 태그 전치부를 설계하고 검증하였다. 문턱전압(threshold voltage) 제거 구조의 전압 체배기, 전류를 이용한 복조 회로로 설계되었으며 파워다운 회로를 추가하여 정류동작의 안정성에 중점을 두었다. PWM(Pulse Width Modulation)을 이용한 변조기를 구조로 입력단에 용량성 임피던스의 변화로 변조 동작을 검증하였다. 삼성 0.18um 공정을 이용하였고, 인식거리는 15m, 평균 소모 전력은 약 60uW이며, 패드를 포함한 칩 사이즈는 $1.22mm^2$이다.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06d
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• pp.97-100
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• 2008

PDoS (Path-based DoS) 공격은 J. Deng에 의해 처음 소개된 DoS 공격의 하나이다. PDoS 공격은 Base Station을 향해 대량의 bogus 패킷을 경로상에 플러딩하여 경로상에 있는 중간 노드들의 배터리 파워를 빠르게 소모를 시켜 수명을 단축시킨다. 그 결과 경로상의 중간 노드들은 수명을 마치게 되어 경로가 마비시켜 전체적으로 네트워크를 마비시킨다. 이런 PDoS 공격을 탐지하기 위해 J. Deng의 one-way hash function을 이용한 탐지방식은 매우 효율적이다. 하지만 공격자가 compromised node을 사용할 경우 이 탐지 기법은 소용이 없어진다. compromised node는 특성상 특별하게 눈에 띄는 비정상 행위를 하지 않는 이상 일반 노드와 구분하기가 힘들며 공격자에 의해 다른 여러 공격에 이용되어 무선 센서 네트워크 보안에 큰 위협이 된다. 이에 본 논문에서는 무선 센서 네트워크상에서 PDoS 공격을 야기하는 compromised node를 탐지하는 방법을 제안한다.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.63-72
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• 2004

The supply voltage has been drop rapidly and the total length of the wire increased exponentially in the nanometer SoC design environment. The ideal supply voltage was dropped sharply by the resistance and parasitic devices which stayed on the kilometers-long wire length. Even worse, it could severely affect the functional behavior of the block of the design. To analyze the effects of the long wire of the SoC while maintaining the accuracy, the modeling of the current and the RC conversion of the parasitic techniques are researched and applied. By these modeling and conversion, the multi-million gates HDTV Chipset can be analyzed within a day. The benchmark analysis of the HDTV SoC showed the superiority to the conventional methods in performance and accuracy.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.47-51
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• 2009

The low latency encoder for high data rate duo-binary turbo codes with tail biting trellises is considered. Encoder hardware architecture is proposed using inherent encoding property of duo-binary turbo codes. And we showed that half of execution time as well as the energy can be reduced with the proposed architecture.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.703-706
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• 2002

최근 컴퓨터 그래픽스 분야에서 보다 현실감 나는 영상을 제공하기 위해, 많은 기하로 구성될 뿐만 아니라 깊이 복잡도가 매우 높은 데이터가 요구되어지고 있다. 또한 기하학적으로 늘어나는 데이터를 실시간에 처리해 줄 수 있는 고성능의 렌더링 시스템에 대한 요구도 높아지고 있다. 이에 본 논문에서는 OpenGL 기반에서 occlusion culling을 1-패스에 처리하여 고성능을 보여주는 렌더링 구조를 제안한다. 이는 2-패스의 기존 구조에서 반복적으로 발생되는 불필요한 연산을 효과적으로 제거하여 성능을 높여주고 파워 소모도 최소로 하고 있다. 실험을 통해 제안 구조가 기존 구조에 비해 $1.2\sim1.5$배 성능 향상을 보임을 알 수 있었다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.22-24
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• 2001

슈퍼스칼라 프로세서에서는 분기 명령의 결과 지연으로 명령의 공급이 중단되는 것을 방지하고 지속적인 파이프라인 처리를 위해서 분기의 결과를 미리 예측하여 명령을 폐치하고 있다. 본 논문에서는 심플스칼라 툴 셋을 사용하여 슈퍼스칼라 프로세서에서 사용되는 대표적인 동적 분기예측 방법 시뮬레이션 환경을 구축한다. 동적 분기예측 방법으로 분기 타겟버퍼(Branch Target Buffer, BTB) 상에서 분기명령의 자기 히스토리에 근거한 BTB 방식과 이전 분기명령의 히스토리와의 상관관계를 고려한 Gshare 분기예측기를 적용 구현한다. 심플스칼라 시뮬레이터에 SPEC95 벤치마크 프로그램을 실행시켜 디자인 파라미터 변화에 따른 분기 예측기의 예측정확도를 실험한다. 또한 BTB와 Gshare 분기예측기를 VHDL로 구현하고 Synopsys 툴을 이용하여 시뮬레이션 및 합성 과정을 거쳐 게이트 크기와 파워 소모량을 측정한다.