• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.234-237
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• 2015

현재 RDBMS는 대부분 블록기반의 스토리지를 사용하는데 오늘날 정형화 되지 않은 데이터 타입에 대한 요청이 많아지고 있어서 오브젝트 스토리지를 사용하려는 연구가 활발히 진행 되고 있다. 그래서 본 논문을 통해 오브젝트 스토리지를 사용하는 RDBMS 환경을 제안한다. 오브젝트 스토리지 중 오픈 소스로 많이 사용되고 있는 Swift와 Ceph를 사용하여 시스템을 구축, 두 시스템간의 파일 및 RDBMS 성능비교를 진행하였다. Swift와 Ceph는 동일한 인터페이스가 아니기에 중간에 새로운 레이어를 추가하여 POSIX 환경에서 테스트가 가능하도록 하였다. 데이터베이스는 Postgresql을 사용하였고 두 시스템 간의 성능측정은 파일벤치마크인 IOzone 그리고 Posgresql에서 지원하는 TPC-B 기반 pgbench를 사용, 노드 확장성과 가상 클라이언트 수를 비교표로 활용하여 실험을 진행하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.777-779
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• 2012

인터넷의 확산으로 인해 전송, 서비스 및 보안과 관련된 많은 장비들이 개발되고 출시되고 있다. 서비스 및 보안과 관련된 장비들은 새로운 개발과 급속한 도입으로 인해 적절한 성능측정방법의 부재로 인해 많은 혼란과 문제들을 가져오기도 했었다. 이에 장비를 도입하는 기관들은 전문 시험기관의 시험과 평가를 거쳐 발행된 성적서나 보고서를 참고하거나 직접 벤치마킹테스트를 거쳐 도입을 결정하고 있다. 본 논문에서는 IP 네트워크 장비들의 성능측정을 위한 방법들을 분석하고 표준으로 제정된 시험 방법론을 분석하여 시스템 성능측정을 위한 메트릭을 제시하고자 한다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.07a
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• pp.449-450
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• 2020

최근 블록체인이 많은 분야에서 활용되고 있다. 본 연구에서는 블록체인과 관련된 개발 도구에 포함된 보안약점을 분석하고 그 보안약점을 진단하기 위한 정보를 기반으로 분류한다. 또한 일부 보안약점의 예를 통하여 진단하기 위한 알고리즘을 llvm의 Clang 도구에 적용하기 위한 방법을 연구한다. 이를 통하여 블록체인과 관련된 보안약점을 분류하고 그에 대한 진단 방법을 연구하였다. 향후 기존 정적 분석 도구를 확장함으로써 진단 성능을 높일 수 있을 것이며, 줄리엣 코드와 같은 벤치마크 테스트를 통해 그 결과를 비교해볼 수 있을 것이다.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1177-1184
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• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.138-144
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• 2010

Tachyon primary system which introduces recently is a high performance supercomputer that composed with AMD Barcelona nodes. In this paper, we will verify the performance and parallel scalability of TachyonIn by using multi-zone NAS Parallel Benchmark(NPB) which is one of a program with hybrid parallel method. To test performance of hybrid parallel execution, B and C classes of BT-MZ in NPB version 3.3 were used. And the parallel scalability test has finished with Tachyon's 1024 processes. It is the first time in Korea to get a result of hybrid parallel computing calculation using more than 1024 processes. Hybrid parallel method in high performance computing system with multi-core technology like Tachyon describes that it can be very efficient and useful parallel performance benchmarks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.11
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• pp.765-770
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• 2020

The turbochargers used widely in diesel and gasoline engines are effective devices to reduce fuel consumption and emissions. In this study, the isentropic turbine efficiency of the steady flow in a twin-scroll turbocharger for the passenger vehicle gasoline engine was analyzed. The cold gas test bench was designed and made. The pressure and temperature of the inlet and exit of the turbine were measured at 60,000, 70,000, 90,000, and 100,000rpm under the steady-state flow. The isentropic turbine efficiency was calculated. The efficiency was the range of 0.53 to 0.57. The BSR and expansion ratio were changed from 0.71 to 0.84 and from 1.24 to 1.72, respectively. The isentropic turbine efficiency decreased with increasing BSR and expansion ratio. The operation of only scroll A or B was compared with that of the twin-scroll turbine. The isentropic efficiency of using only scroll B was higher than those of only scroll A at 60,000rpm. The isentropic efficiency of using only scroll A was higher than those of only scroll B at 100,000rpm. Therefore, the twin-scroll turbine used in this study is operating effectively in the wide speed range.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.2
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• pp.386-391
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• 2021

Turbocharging is becoming a key technology for both diesel and gasoline engines. Regarding gasoline engines, turbocharging can help reduce carbon dioxide (CO2) emissions when used in conjunction with other technologies. This paper presents measurements of the turbine efficiency of pulsating flow in a twin-scroll turbocharger for gasoline engines. A cold gas test bench with a pulse generator was manufactured. The turbine efficiencies were calculated using the measured data of the instantaneous pressure and temperature of the inlet and exit of the turbine. The measurements were carried out at turbine speeds from 60,000 to 100,000 rpm under a pulsating flow of 25.0 Hz and 33.0 Hz. The turbine efficiencies ranged from 0.517 to 0.544. At the pulse frequency, 33.3 Hz, the variations in efficiency were 7.7% and 2.6% at turbine speeds of 60,000 rpm and 100,000 rpm, respectively. The turbine efficiency of the pulsating flow compared to those of steady flow was 7.0% and 3.0% lower at a turbine speed of 60,000 rpm and 100,000 rpm, respectively. The pulsating flow deteriorated the turbine efficiency, but the effects of pulsating flow decreased with increasing turbine speed.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.24 no.3
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• pp.171-179
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• 2014

Sunroof buffeting is one of the most critical issues in the vehicle wind noise phenomena. The experimental approach to solve this issue typically requires a lot of time and resources. To reduce time and cost, the numerical approach could be taken, which can also privide more insights into physical phenomena involved in sunroof buffeting, only if the accuracy in its predictions are guranteed. The benchmark test of various numerical solvers is carried out for the buffeting behavior of a simplified vehicle body, the Hyundai simplified model(HSM). The results of each solver are compared to the experimental measurements in a Hyundai aeroacoustic wind tunnel(HAWT) at various wind speeds. In particular, acoustic response tests were performed and the results were provided prior to all simulations in order to consider the real world effects that could introduce discrepancies between the numerical and experimental approaches. Through this study, most solvers can demonstrate an acceptable accuracy level for actual commercial development and high precision experimental data and computational prediction priories can be shared in order to promote the numerical accuracy level of each numerical solver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.46-56
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• 2002

In this paper, we describe a hardware-software co-verification methodology and environment in developing a mobile station modem chip for cdma2000 1x which is one of the 3rd generation mobile communication standards. By constructing an efficient co-verification environment for a register-transfer-level hardware model and a physical-layer software model combining a channel link simulator and a versatile test-bench, we can drastically reduce both time and cost for developing a complex three-million-gate class system integrated circuit.