• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.383-383
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• 2012

전자소자 및 광전소자의 최적화 조건을 확립하기 위해 반도체 나노양자구조의 물리적 현상에 대한 연구가 활발히 진행되고 있다. 반도체 양자세선은 일차원 구조의 기초 물리 특성 관찰과 소자로서의 응용 가치가 높다. 양자세선을 사용한 단전자 트랜지스터, 공명터널 다이오드, 발광다이오드, 광탐지기 및 레이저 소자 제작과 관련한 연구가 활발히 진행 중에 있다. 나노양자구조들 중에서 양자우물과 양자점에 대한 실험적 및 이론적 연구가 많이 진행되었으나, 복잡한 공정 과정과 물리적 이론의 복잡함으로 양자세선에 대한 연구는 상대적으로 미흡하다. 양자세선을 이용한 전자소자와 광전소자의 효율을 증진하기 위해서는 양자세선의 전자적 성질에 대한 연구가 중요하다. 본 연구에서는 InAs/InP 양자세선에 대한 기저상태와 여기상태의 전하분포, 부띠천이 및 전자적 성질을 고찰하였다. 가변 메시 유한 차분법을 이용하여 양자세선의 이산적 모델을 확립하여 변형효과가 양자세선 구조에서 부띠에 영향을 주는지 조사하였다. 변형효과와 비포물선효과를 고려한 슈뢰딩거 방정식을 사용하여 변형 포텐셜을 계산하였으며 양자세선의 포텐셜 변화를 관찰하였다. 양자세선의 포텐셜 변화에 따라 전하구속분포, 에너지 준위 및 파동 함수를 계산하였다. 기저상태의 부띠 간에 발생하는 천이와 여기상태의 부띠 간에 발생하는 부띠 간의 엑시톤 천이 에너지 값을 계산하였다. 계산한 부띠 에너지 천이 값이 광루미네센스로 측정한 엑시톤 천이와 잘 일치하였다. 이 결과는 양자세센의 이차원적인 전자적 구조를 이해하고 양자세선을 사용하여 제작된 전자소자 및 광전소자의 전자적 성질을 연구하는데 도움을 주며, 저전력 나노양자소자를 제작하는 기초지식을 제공하는 중요한 역할을 할 것이다.

• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.197-202
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• 2023

This paper presents the design method and electrical characteristics of a high-efficiency power amplifier for a 50 Watts class repeater applied to a 5G system and used in in-building, subway, and tunnel. GaN was used for the termination transistor of the power amplifier designed here, and intermodulation signals were removed using DPD to satisfy linearity. In addition, in order to handle various requirements such as amplifier gain control and alarm processing required in the 5G system, the microprocessor is designed to exist inside the power amplifier. The amplifier manufactured to confirm the electrical performance of the power amplifier satisfying these conditions satisfied 46.5 dBm and the overall efficiency of the amplifier was 37%, and it was confirmed that it satisfied various alarm conditions and electrical characteristics required by telecommunication companies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.