• The Journal of the Korea Contents Association
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• v.9 no.9
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• pp.90-96
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• 2009

The aim of the research is that disease database of the glycosuria and heart's blood is designed to manage the condition of the glycosuria and heart's blood patients periodically and continuously. Also we integrate patient database of existing OCS, PACS, EMR, ERP etc. and support optimal service timely that the patients want through intelligent integrated interface environment. For this, we will develop customized medical information convergence system. We construct intelligent database for disease of the glycosuria and heart's blood. And we support data integration environment for connection with existing systems - OCS, EMR, PACS etc. Also, in consideration of QoS, reliability, and expandability of customized medical information convergence system, we will design H/W, S/W, and data compatibility method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2032-2038
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• 2007

Embedded Controller which controls whole system is most important part of embedded system. Nowadays, new technique called SoC is more using than ASIC. But SoC have some problems. Because of long development time and high cost, it is hard to applying SoC to small and medium enterprise. So many companies use IP technique combined with embedded processor. High resolution inkjet marking system is printing system with embedded controller. It is used in various part of industry. But it has many problems such as printing quality, marking errors, system faults and so on. In this paper, we designed and implemented IP that can solve the printing quality problems. We analyzed total-logic-elements and timing by simulation. As a result of simulation, we could verified that output signals satisfied reference timing. Appling IP to high resolution inkjet marking system, we could get good quality printing message.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1405-1410
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• 2018

The Ringer's Solution used in medical institutions is one of the injections helpful for recovering the body condition from fever or dehydration by supplying the water to the body. The medical staffs frequently check the amount of Ringer's Solution prescribed for the relevant patient to check the time for replacing the Ringer's Solution. However, currently, many nurses experience the excessive workload because of the insufficient workforce and lots of workload assigned to each of the nurses; so the they cannot provide the high-quality medical services to patients and guardians. In order to solve this problem, this thesis designed and realized the Ringer's Solution replacement time control system through the non-contacting sensor, IoT device using WiFi, and OCS interlock. Thus, this study is expected to be able to efficiently operate the Ringer's Solution replacement work and also to provide the high-quality medical service to patients and guardians by automatically notifying the timing of Ringer's Solution replacement to medical staffs, and omitting the inefficient intermediate step in the past.

• Journal of Digital Convergence
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• v.16 no.12
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• pp.309-315
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• 2018

In this paper, propose an efficient arc detection and control method to achieve fast machining speed, improved precision and surface roughness in discharge machining, especially for carbide and hard material processing and metal processing using discharge phenomenon as energy. A single discharge waveform is divided into three sections of Td (Time-Delay), Ton (Time-on) and Toff (Time-off) and the gate control timing is simulated using the HDL language. In this paper, we analyze the effect of the gap between the electrode and the workpiece on the machining results by determining the operation of the servo mechanism by sampling the Td section through the comparator circuit. As a result of the analysis, the Td section of the formed waveform was more precisely sampled at a high speed and the results were improved when applied to the gap control between the electrode and the workpiece.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.139-149
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• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.

• Journal of Industrial Convergence
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• v.20 no.6
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• pp.135-140
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• 2022

In the domestic stock market, the capital market opened in January 1992, and the proportion of foreign capital has steadily increased, accounting for 30% of the domestic market in Overall stock market trend infers that the domestic stock market is more influenced by foreign issues than domestic issues. The trading trend of foreign capital displays a similar flow to exchange rate fluctuations,; thus, preparing an investment strategy by using the Pearson analyzing method the effect of exchange rates of foreign capital trading, fluctuations in exchange rates, and predicting one of the macroeconomic indicators will yield high returns in the stock market. Therefore, this research was conducted to help investment by predicting foreign variables comparing and analyzing exchange rates and foreign capital trading patterns, and predicting appropriate time for buying and selling.