• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.327-332
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• 2012

In this paper, we analyzed the influence of different observation stations distributions on satellite clock offset estimation based on the PANDA software. The result shows that, when the distance between stations is shorter than 200km, the correlation of troposphere parameter and satellite clock offset parameter is strong, the accuracy of satellite clock offset estimation will be up to 0.8ns; when the distance between stations is up to 500km, as the correction of troposphere parameter and satellite clock offset parameter is significantly reduced, and the two kinds of parameters can be distinguished.

• ETRI Journal
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• v.8 no.2
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• pp.45-52
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• 1986

교환망이 점차로 디지틀화 되면서 네트워크내의 클럭 주파수의 불일치에 의해 야기되는 slip 발생에 따른 정보손실은 중요한 문제점으로 대두되었으며 모든 디지틀 교환기는 네트워크내의 기준 주파수에 자체 클럭을 동기시키기 위한 망동기 기능을 수용하며 silp 발생을 방지하고 있다. TDX-1에서는 국내 교환망 동기 체계에 적합한 동기회로계를 개발하여 망동기를 성취하고 있으며 본고는 이 회로계의 특성에 대해 논하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.644-649
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• 2003

Novel 622Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35$\mu\textrm{m}$ CMOS process technology. Lock is accomplished on the first data transition and data are sampled in the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400Mbps-680Mbps burst mode input data without error.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.07a
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• pp.69-72
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• 2013

본 논문은 TPSN 알고리즘의 시각 동기화 오차를 개선하기 위하여 Imote2 센서 노드의 클럭 드리프트 특성을 적용하는 개선된 TPSN 알고리즘을 제안한다. 클럭 드리프트의 원인은 주로 수정발진기에 기인한다. 본 연구에서는 온도 및 습도 등 환경 조건이 비슷할 경우에 드리프트가 크게 차이나지 않는다는 실험 결과에 따라 드리프트의 평균값을 구하고 이를 TPSN 동기화 오차 보정에 사용한다. 이때 적용되는 드리프트 특성 값은 센서 노드 설치 이전에 미리 측정하여야 한다. 실험을 통하여 본 논문에서 제안한 개선된 TPSN 알고리즘이 동기화 오차 개선에 효과적임을 확인하였다.

• The KIPS Transactions:PartC
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• v.13C no.3 s.106
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• pp.303-310
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• 2006

This paper is to execute a study for characteristic analysis of synchronization clock and maximum network node number with various clock states, normal, SPT, LPT, in NG-SDH networks. Through the simulations, maximum network node numbers showed from 42 to 38 nodes in normal state. In SPT state, maximum network node numbers, when the last NE network applied to only SPT state, presented from 19 to 4 nodes, much less than normal state. Node numbers to meet specification in case of occurrence of SPT state in all NE networks decreased greatly. In LPT state, all maximum node numbers, when the last NE network applied to only LPT state, presented more than 50 nodes, and the results in case of occurrence of LPT state in all NE networks were also identified. However, node numbers to meet specification in case of LPT state in all DOTS networks were few large with difference between LPT and normal or SPT state.

• Journal of IKEEE
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• v.13 no.2
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• pp.118-125
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• 2009

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.227-236
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• 2005

We study, in terms of VoIP user assessment of voice quality, the synchronization of measurement system is important. Commonly the synchronization system uses NTP(Network Time Protocol) or GPS(Global Positioning System), these synchronization method has time error of distance, system overhead of data processing, and system specialized clock error. we propose and implement the synchronization method to correct time error between two measurement system in the internet. So the time synchronization of systems can get time error, then user assessment of voice quality become reliable.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1277-1281
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• 2005

FPGA has been widely used in communication system. In this paper, we made 10 layers PCB on protection of signal noise and data lose with FPGA. We analyzed about change of the data transmission speed and length according to input frequency. The length of transmission line from FPGA's output-pin to output-port on PCB board is 13cm and extended lengths for test are 30cm, 60cm and 10cm. We knew that data can be stably transmitted to 100Mbps at transmission line length of 30cm.

• Korean Journal of Optics and Photonics
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• v.17 no.1
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• pp.68-74
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• 2006

We have extracted an optical clock signal from a return-to-zero(RZ) pseudorandom bit sequence(PRBS) and non-return-to-zero(NRZ) PRBS data in a pulsation multi-section laser diode with DFB reflector. The ms timing jitter achieved less than 1 ps for the input 11.727 Gbit/s RZ PRBS and NRZ PRBS data. The PRE data wasconverted from the NRZ data using an NRZ to pseudo-return to zero(PRZ) converter module. The optical clock was extracted from the PRZ data which contains the clock components. Although the input PRZ data gives a timing jitter of 2 ps, the extracted clock has timing jitter of ${\~}$1 ps.