• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.14-24
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• 2006

The terrestrial-DMB (T-DMB) provides one-way broadcasting service in intial phase and two-way interactive data services through a return channel of mobile communications network are commercialized recently. The possible evolution of the T-DMB will be fully convergence between the T-DMB and other communication services such as telematics, RFID and so on. From this evolution point of view, a framework should be defined for supporting telematics and RFID applications on T-BMB platform. In this paper, we propose an integrated service model that could support RFID application services on the interactive T-DMB. To realize the model, we design a service scenario, a network reference model, functionalities of each entity, a data transmission mechanism messages, and coding rules. The service model could allow users to support the identical RFID application services over the T-DMB network even if T-DMB terminal doesn't have RFID reader capability. In addition, in the case for providing the interactive TTI(Traffic and Travel Information)service, users could utilize the current location based RFID application service using by the TPEG-Location application that forms the basis of user location referencing. The messages structure is designed by following TPEG standardization

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.862-870
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• 2015

The RDO (Rate Distortion Optimization) process of HEVC results in good coding efficiency, but relatively requires much encoding time. In order to reduce the encoding time of RDO process, this paper proposes a method of fast intra prediction mode decision using DCT coefficients distributions and the existence of DCT coefficients. The proposed fast Intra coding sets the number of intra prediction mode candidates to three(3) from the RMD (Rough Mode Decision) process in HM16.0 reference SW and reduces the number of candidates one more time by investigating DCT coefficients distribution. After that, if there exists a quantized DCT block having all zero coefficient values for a specific candidate before the RDO process, the candidate is chosen without the RDO process. The proposed method reduces the encoder complexity on average 46%, while the coding efficiency is 2.1% decreased compared with the HEVC encoder.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.725-733
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• 2012

MPEG and VCEG have constituted a collaboration team called JCT-VC(Joint Collaborative Team on Video Coding) and have been developing the HEVC(High Efficiency Video Coding) standard. The next generation video coding standard HEVC shows higher compression rate compared with the H.264/AVC standard, but the encoder computational complexity of the HEVC encoder is significantly high. In order to reduce this computational complexity in the HEVC encoder, a fast prediction unit decision is proposed. The proposed fast prediction unit decision method reduces the encoder complexity by skipping the remaining prediction units if the current prediction unit does not have any non-zero quantized transform coefficient. The proposed method reduces the encoder computational complexity by 50.3% comparing with HM6.0 but it maintains the same level of coding efficiency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.39-54
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• 2012

Picture Archiving and Communication System (PACS) has been planted as one of the key infrastructures with an overall improvement in standards of medical informationization and the stream of digital hospitalization in recent days. The kind and data of digital medical imagery are also increasing rapidly in volume. This trend emphasizes the medical image compression for storing large-scale medical image data. Digital Imaging and Communications in Medicine (DICOM), de facto standard in digital medical imagery, specifies Run Length Encode (RLE), which is the typical lossless data compressing technique, for the medical image compression. However, the RLE is not appropriate approach for medical image data with bilateral symmetry of the human organism. we suggest two preprocessing algorithms that detect interested area, the minimum bounding rectangle, in a medical image to enhance data compression efficiency and that re-code image pixel values to reduce data size according to the symmetry characteristics in the interested area, and also presents an improved image compression technique for brain CT imagery with high bilateral symmetry. As the result of experiment, the suggested approach shows higher data compression ratio than the RLE compression in the DICOM standard without detecting interested area in images.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.106-113
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• 2003

The modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT) are employed in subband/transform coding schemes as the analysis/synthesis filter bank based on time domain aliasing cancellation (TDAC). And the MDCT and IMDCT are the most computational intensive operations in layer III of the MPEG audio coding standard. In this paper, we propose a new efficient algorithm for the MDCT/IMDCT computation in various audio coding systems. It is based on the MDCT/IMDCT computation algorithm using the discrete cosine transforms (DCTs), and It employs two discrete cosine transform of type II (DCT-II) to compute the MDCT/IMDCT In addition, it takes advantage of ability in calculating the MDCT/IMDCT computation, where the length of a data block Is divisible by 4. The Proposed algorithm in this paper requires less calculation complexity than the existing method does. Also, it can be implemented by the parallel structure, therefore its structure is particularly suitable for VLSI realization

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.57-63
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• 2008

Recently, OGC(Open Geospatial Consortium) take the lead in SWE(Sensor Web Enablement) research that collection various context information from sensor networks and show it on map by web. OGC SWE WG(Working Group) defines a standard encoding about realtime spatiotemporal appear geographical feature, sensing data and support web services. This paper proposes a visualization scheme of sensing data based location on 2D maps. We show realtime sensing data on moving node that mapping GPS data on map. First, we present an algorithm and procedure that location information change to position of maps for visualization sensing data based on 2D maps. For verifying that algorithm and scheme, we design and implement a program that collecting GPS data and sensing data, and displaying application on 2D maps. Therefore we confirm effective visualization on maps based on web which realtime image and sensing data collected from sensor network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.79-85
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• 2010

In video standards such as H.264/AVC, motion estimation (ME) / compensation (MC) is regarded as a vital component in a video coder as it consumes a large amount of computation resources. The full search technique, which is used in general video codecs, gives the highest visual quality but also has the problem of significant computational load. To solve this problem, many fast algorithm has benn proposed. Among them, NPDS show that can maintain its video quality very close to the full search technique while achieving computation reduction by using a halfway-stop technique in the calculation of block distortion measure. In this paper, we proposed algorithm by determining minimum distortion measure with predictive motion vector and using the new search order. As the result, we can check that the proposed algorithm reduces the computational load 95% in average compared to the full search, respectively with the PSNR lost about 0.04dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1073-1081
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• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.