• Proceedings of the Korean Information Science Society Conference
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• 2006.06c
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• pp.67-69
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• 2006

기술의 발달로 CPU의 속도는 메모리의 속도에 비해 급속한 속도로 발전하였다. 그 결과 데이터베이스 시스템을 포함한 다른 컴퓨터 응용분야에서 메모리의 접근속도가 병목현상을 일으키게 되었다. 그래서 메모리의 접근 속도를 줄이기 위해 캐시 메모리가 도입되었고, 이를 활용하여 CPU 캐시를 효율적으로 활용하기 위한 많은 연구들이 있었고, 그 중 하나가 CST(Cache Sensitive T-tree)이다. 이 인덱스 구조는 점 검색(Point search)에서는 좋은 성능을 보이지만 범위 검색(range search)에서는 그렇지 못하다. 본 논문에서는 범위 검색(range search)을 위한 CST-tree에 대한 구축 기법을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.44-45
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• 2013

전 세계의 스마트폰 보급률이 증가와 함께 새로운 형태의 스마트 워치, 구글 글래스 등의 모바일 장비들이 등장하고 있다. 이는 제한된 자원을 사용하는 스마트폰 환경에서 효율적으로 CPU, 메모리, 저장 장치들을 효과적으로 사용하기 위한 연구를 필요로 한다. 이에 본 논문에서는 안드로이드 환경에서 부족 메모리의 공간 확보를 위해 동일한 내용의 페이지 캐시를 찾고, 중복 제거하는 기법을 제안한다. 이는 부족한 메모리 공간 확보와 캐시를 지속하여 I/O 연산의 빈도를 줄여 스마트폰 성능 향상을 가져올 것으로 기대된다.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.247-251
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• 2010

Using SCM in storage systems introduce new potentials for improving I/O performance and reliability. In this paper, we study the use of SCM as a buffer cache that guarantees transactional unit writes. Our proposed method can improve storage system reliability and performance at the same time and can recover the storage system immediately upon a system crash. The Proposed method is based on the LINUX JBD(Journaling Block Device), thus reliability is equivalent to JBD. In our experiments, the file system that adopts our method shows better I/O performance even while guaranteeing high reliability and shows fast file system recovery time (about 0.2 seconds).

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.101-110
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• 1997

SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

• KIISE Transactions on Computing Practices
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• v.23 no.9
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• pp.564-571
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• 2017

The burst loading of a pre-created cache-image is an effective method to reduce the instruction cache misses in the early stage of the program execution. It is useful to alleviate the performance degradation as well as the energy inefficiency, which is induced by the concentrated cold misses at the instruction cache. However, there are some defects, including software overhead on the compiler and installer. Furthermore, there are several mismatches as a result of the dynamic properties for specific applications. This paper addresses these issues and proposes a cache-image maintenance/recreation policy that can conduct dynamic management using a hardware-assisted method. The results of the simulation show that the proposed method can maintain the cache-image with a proper size and validity.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.13-21
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• 2013

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.293-303
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• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10b
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• pp.52-54
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• 2004

이동객체의 위치 정보는 데이터의 양이 방대하고, 객체의 위치가 변경될 매마다 계속적인 갱신연산이 요구되어진다. 이러한 갱신 연산에서 디스크 접근비용을 최소화하기 위해 최근 Lazy Update R-tree(LUR-tree)가 제안되었다. 그러나 디스크 기반의 색인은 검색 및 갱신 연산의 실시간 처리를 보장할 수 없기 때문에 메인 메모리에서 이동객체의 위치 정보를 유지하는 것이 필요하다. 본 논문에서는 디스크 기반의 LUR-tree를 MBR 압축을 통해 캐시에 최적화되도록 변형한 색인기법을 제안한다. MBR 압축기법은 부모 노드로의 상대적 위치로 표현된 엔트리의 MBR을 변환함수를 통해 2,4,8 바이트의 정수로 변환한다. 제안된 색인은 변환된 MBR의 크기에 따라 엔트리를 동적 할당함으로써, 상위노드에서는 키 비교 회수를 줄이고, 단말 노드로 갈수록 키 비교 횟수는 늘어나지만, 캐시 미스를 줄일 수 있다는 장점으로 인해 검색 및 갱신 성능을 전체적으로 향상시킨다

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1363-1366
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• 2006

본 논문에서는 각각의 그래픽 가속기에 픽셀 캐시를 사용가능 하게 하면서 성능을 증가시키고 일관성 문제를 해결하는 병렬 렌더링 프로세서를 제안한다. 제안하는 구조에서는 픽셀 캐시 미스에 의한 latency를 감소시켰다. 이러한 2가지 성과를 위하여 현재의 새로운 픽셀 캐시 구조에 효과적인 메모리 구조를 포함시켰다. 실험 결과는 제안하는 구조가 16개 이상의 레스터라이저에서 거의 선형적으로 속도 향상을 가져옴을 보여준다..

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.40-46
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• 2003

The high-performance processors have recently employed sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. For the query processing of database management systems, those hardware characteristics are the important research issue. The latest works show that the cache miss penalty between main memory and CPU becomes new bottlenecks and the branch misprediction causes serious resource-waste. An effcient algorithm for query processing of aggregate functions considering these hardware characteristics was proposed in this dissertation.