• The Journal of Korean Institute of Information Technology
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• v.16 no.11
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• pp.61-68
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• 2018

This paper describes design of a 10.525 GHz self oscillating mixer semiconductor IC chip combining voltage controlled oscillator and frequency mixer using silicon CMOS technology for Doppler radar applications. The p-core type VCO included in the self oscillating mixer minimizes the noise contained in the transmitted signal. This noise minimization increases the sensing distance and acts in a direction favorable to the reaching distance and the sensitivity of the motion detection sensor. Simulation results for phase noise show that a VCO designed as a P-core has a noise characteristic of -106.008 dBc / Hz at 1 MHz offset and -140.735 dBc / Hz at 25 MHz offset compared to a VCO designed with N-core and NP-core showed excellent noise characteristics. If a self-oscillating mixer is implemented using a p-core designed VCO in this study, a motion sensor with excellent range and reach sensitivity will be produced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.520-523
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• 2016

This paper describes a DC-DC converter with MPPT control for thermoelectric energy harvesting. The designed circuit converts low voltage harvested from a thermoelectric generator into higher voltage for powering a load. A start-up circuit supplies VDD to a controller, and the controller turns on and off a NMOS switch of a main-boost converter. The converter supplies the boosted voltage to the load through the switch operation. Bulk-driven comparators can do the comparison under low voltage condition and are used for voltage regulation. Also, bulk-driven comparators raise system's efficiency. A peak conversion efficiency of 76% is achieved. The proposed circuit is designed in a 0.35um CMOS technology and its functionality has been verified through simulations. The designed chip occupies $933um{\times}769um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.267-270
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• 2014

This paper presents a CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter and a DC-DC boost converter. The AC-DC converter rectifies the AC signals from vibration devices(PZT), and the DC-DC boost converter generates a boosted and regulated output at a predefined level. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. A MPPT(Maximum Power Point Tracking) control is also employed to harvest the maximum power from the PZT. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $530um{\times}325um$. Simulation results shows that the maximum efficiencies of the AC-DC converter and DC-DC boost converter are 97.7% and 89.2%, respectively. The maximum efficiency of the entire system is 87.2%.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.564-569
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• 2021

In this paper, for the typical LED and the tilted LED, when there is no electrode, when 20% absorption (80% reflection) occurs at the electrode, and when 60% absorption (40% reflection) occurs at the electrode, the effect of the absorption at the electrode and the height of the active region on the photon extraction efficiency and the mean photon path length was investigated, and an appropriate height of the active region was proposed. In a typical LED, as the absorption of the electrode increases, the photon extraction efficiency decreases from 18% to 15% and 13%, and the photon extraction efficiency is highest when the height of the active area is located in the center between the two electrodes. In the tilted LED, as the absorption of the electrode increases, the photon extraction efficiency decreases from 38% to 33% and 25%, and the photon extraction efficiency is highest when the height of the active area is located in the center between the two electrodes. The tilted LED can increase the photon extraction efficiency more than twice than that of a typical LED, where photons are trapped inside the chip due to total reflection.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.23 no.2
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• pp.91-96
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• 2022

At the current camera-based technology level, sensor-based basic life pattern recognition technology has to suffer inconvenience to obtain accurate data, and commercial band products are difficult to collect accurate data, and cannot take into account the motive, cause, and psychological effect of behavior. the current situation. In this paper, radar technology for life pattern recognition is a technology that measures the distance, speed, and angle with an object by transmitting a waveform designed to detect nearby people or objects in daily life and processing the reflected received signal. It was designed to supplement issues such as privacy protection in the existing image-based service by applying it. For the implementation of the proposed system, based on TI IWR1642 chip, RF chipset control for 60GHz band millimeter wave FMCW transmission/reception, module development for distance/speed/angle detection, and technology including signal processing software were implemented. It is expected that analysis of individual life patterns will be possible by calculating self-management and behavior sequences by extracting personalized life patterns through quantitative analysis of life patterns as meta-analysis of living information in security and safe guards application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.1
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• pp.35-42
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• 2024

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.