• Journal of IKEEE
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• v.18 no.3
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• pp.349-355
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• 2014

In semiconductor IP reuse, precise understanding of semiconductor IP interfaces is essential for integrated chip design. However, in general, these interfaces are described in the original designer's description style. Furthermore, their description method are not unified, so it is very difficult for the chip integration designer to understand them. This paper proposes a standardized description method of semiconductor IP interfaces. It consists of 9 items such as IP information, description level, model provision, data type, interface information, port information, signal information, protocol information, and source file. The proposed method helps the chip integration designer to understand semiconductor IP interfaces and to integrate them into a single chip.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.202-211
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• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1925-1926
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• 2008

본 논문에서는 UHF TV방송 전 대역 Ch.14(473MHz)$\sim$Ch.69(803MHz)까지의 모든 채널에서 동작하는 유도결합구조의 RF동조회로를 설계하였다. 기존 자기결합구조의 RF동조회로는 PCB 양면을 사용하여야 하고 수작업으로 Air Coil 간격을 조절해야만 한다. 부품의 집적화와 양산 효율성 측면에서 자기결합구조의 단점을 해결할 수 있도록 하기 위해 본 논문에서 제안한 유도결합구조는 수동부품인 칩인덕터와 칩커패시터 및 가변용량 다이오드만을 사용하여 RF동조회로를 설계하였다. 칩인덕터는 Air Coil에 비해 낮은 소자 Q값을 가진다. 상대적으로 낮은 Q값을 갖는 칩인덕터를 사용하기 때문에 이를 보완하기 위해 Peaking용 칩인덕터를 설계 디자인에 적용하였다. 가변형 대역통과필터로 동작하기 위해 자기결합구조와 동일하게 가변용량 다이오드를 이용하였다. UHF TV방송 전 대역(470$\sim$806MHz)에서 -2.88 $\sim$ -3.97dB의 삽입손실 특성 및 -8dB 이상의 반사손실 특성과 330MHz의 중심주파수 변화 범위를 갖는다. 현재 상용중인 지상파 튜너에 적용되고 있는 자기결합구조의 RF동조회로를 대치하여 적용될 수 있을 것이다.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.11-19
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• 2000

This research deals with the implementation procedures of a chorus processing DSP for karaoke system. It is necessary to compress the chorus data to store as many choruses as we can. We apply MPEG-1 audio algorithm to compress the chorus data. And the chorus system must be accompanied with the karaoke that can change the key and the tempo. So the chorus DSP must be able to change the key and tempo of the chorus data. We apply SOLA (Synchronized Overlap and Add) to do it. We designed the chorus DSP that can compress the chorus, change the key and tempo. And we verified the chorus DSP logic using FPGA. The used FPGA are two FLEX10K100s made by ALTERA. Finally we make the ASIC chip of chorus DSP and verify its operation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.3
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• pp.301-307
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• 2002

A multilayer ceramic chip antenna with helical structure is analyzed to enhance the narrow bandwidth of conventional ceramic chip antennas. The simulations are performed by HFSS to verify the effects of structural parameters on impedance bandwidth. The multilayer ceramic chip antennas consist of a rectangular-parallelepiped ceramic body$({\varepsilon}_r=7.8,\; tan\; {\delta}=0.0043)$ and helical conductor patterns are embedded in the ceramic body using LTCC-MLC technology. 3D structure design of the multilayer ceramic chip antenna suitable for IMT-2000 (1,920~2,170 MHz) handset has been implemented, and experimental results are presented and discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.131-135
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• 2002

In this project, we have developed various techniques for subminiaturization, surface implementation, high frequency design, small-sizes SMD, performance test and applications of ultra small chip antenna, which is a core component for the personal communication systems. We also obtained base techniques for the next-generation ultra small chip antenna design and fabrication techniques for an internationally competitive subminiature ultra small chip antenna. Center frequency is 2442.5MHz(Type), return loss is -10dB max, VSWR is 2max, xy max gain is -2dB min, size is 0.05ccmax.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

• Journal of Biomedical Engineering Research
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• v.18 no.4
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.