• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.68-68
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• 2004

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.143-143
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• 1996

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.321-325
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• 2009

The detection process of defective tags in most of Korean domestic RFID manufacturing companies is handled or treated by on-hand processing after the job of chip bonding, so it has been requesting to reduce the time and cost for manufacturing of RFID tags. Therefore, in this paper, we design and implement the system to perform the functionality of detection of defective tags after the process of chip bonding, and so provide the basis of a related software to establish the foundation of a automation system for the detection of defected RFID tags which is requested in the related Korean domestic industrial field. The developed system in this paper shows the enhancement of 700% in processing speed and 100% in detection rate of defective tags, comparing to the method of on-hand processing.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.7-13
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• 2007

In the optical module for optical communications, the flip chip bonding is used fer the precise alignment of the optical fiber and optical device. In flip chip bonding, the optical device is aligned and welded while observing the alignment mark of substrate and chip by using flip chip bonder in order to bond the optical device at the exact position. In this research, optical passive alignment method of photodiode(PD) flip chip bonding is suggested for low cost optical subassembly. By using the visible He-Ne laser (633nm wavelength), photodiode is easily aligned with emitting spot on the optical fiber with the help of stereoscopic alignment system. We compensated wavelength dependent deviation about 4m to find out real alignment position of 1550nm input laser by ray tracing. The maximum optical coupling efficiency between the optical fiber and photodiode was about 23.3%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.158-158
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• 2008

모바일 정보통신기기를 중심으로 실장모듈의 초소형화, 고집적화로 인해 접속단자의 피치가 점점 미세화 됨에 따라 플립칩 본딩용 접착제에 함유되는 무기충전제인 실리카 필러의 크기도 미세화되고 있다. 본 연구에서는 NCP (non-conductive paste)의 실리카 필러의 크기가 COB(chip-on-board) 플립칩 패키지의 신뢰성에 미치는 영향을 조사하였다. 실험에 사용된 실리카 필러는 Fused silica 3 종과 Fumed silica 3종이며 response surface 실험계획법에 따라 혼합하여 최적의 혼합비를 정하였다. 테스트베드로 사용된 실리콘 다이는 투께 $700{\mu}m$, 면적 5.2$\times$7.2mm로 $50\times50{\mu}m$ 크기의 Au 도금범프를 $100{\mu}m$ 피치, peripheral 방식으로 형성시켰으며, 기판은 패드를 Sn으로 finish 하였다. 기판을 플라즈마 전처리 후 Panasonic FCB-3 플립칩 본더를 이용하여 플립칩 본딩을 수행하였다. 패키지의 신뢰성 평가를 위해 $-40^{\circ}C{\sim}80^{\circ}C$의 열충격시험과 $85^{\circ}C$/85%R.H.의 고온고습시험을 수행하였으며 Die shear를 통한 접합 강도와 4-point probe를 통한 접속저항을 측정하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.177-180
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• 2003

초 박형 실리콘 칩을 이용하여 실리콘 칩들을 포함한 모듈 전체가 굽힘이 자유로운 유연 패키징 기술을 구현하였으며 bending test와 FEA를 통해 초 박형 실리콘 칩의 기계적 특성을 살펴보았다. 초 박형 실리콘칩$(t<30{\mu}m)$은 표면손상의 가능성을 배제하기 위해 화학적 thinning 방법을 이용하여 제작되었으며 열압착 방식에 의해 $Kapton^{(R)}$에 바로 실장 되었다. 실리콘칩과 $Kapton^{(R)}$ 기판간의 단차가 적기 때문에 전기도금 방식으로 전기적 결선을 이룰 수 있었다. 이러한 방식의 패키징은 이러한 공정은 flip chip 공정에 비해 공정 간단하고 wire 본딩과 달리 표면 단차 적다. 따라서 연성회로 기관을 비롯한 인쇄회로기판의 표면뿐만 아니라 기판 자체에 삽임이 가능하여 패키징 밀도 증가를 기대할 수 있으며 실질적인 실장 가능면적을 극대화 할 수 있다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.649-657
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• 2008

This paper describes the optimized output performances such as output power and the third order intermodulation in GaN high power transistor packages which consist of chip die, chip capacitors, and wire bonding. The optimized output power according to wire bonding techniques, and third order intermodulation performances according to wire bonding and bias conditions are discussed. In addition, it is shown through the nonlinear simulation that how the output performances are sensitive to the inductance values which are realized by wire bonding for matching network in the limited package area.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.43-48
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• 2004

Electromigration of Sn-3.5Ag-0.5Cu solder bumps was investigated with current densities of $3{\~}4{\times}10^4 A/cm^2$ at temperatures of $130{\~}160^{\circ}C$ using flip chip specimens which consisted of upper Si chip and lower Si substrate. Electromigration failure of the Sn-3.5Ag-0.5Cu solder bump occurred with complete consumption of Cu UBM and void formation at cathode side of the solder bump. The activation energies for electromigration of the Sn-3.5Ag-0.5Cu solder bump were measured as 0.61 eV at current density of $3{\times}10^4 A/cm^2$, 0.63 eV at $3.5{\times}10^4 A/cm^2$, and 0.77 eV at $4{\times}10^4 A/cm^2$, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.467-468
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• 2012