• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.10a
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• pp.91-91
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• 2003

• Transactions of the Korean Society of Mechanical Engineers
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• v.15 no.1
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• pp.139-144
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• 1991

Chip flow angle is one of the important factors to be determined for the scheme of Chip Control. Up to now, however, a dependable way to predict the chip flow angle in practical cutting has not been established satisfactorily. In this paper a rather simple theoretical prediction of chip flow angle is tried based on some already widely confirmed hypotheses. The developed equation of chip flow angle contains the parameters of depth of cut d, feed rate f, nose radius $r_{n}$ side cutting edge angle $C_{s}$, side rake angle .alpha.$_{s}$ and back rake angle .alpha.$_{b}$. Theoretical results of chip flow angle given by this study bas been shown in a good agreement with experimental ones.s.s.s.s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.586-589
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• 2004

Ni 내부전극을 적용한 X7R의 온도특성을 가지는 고압용 적층 칩 캐패시터를 설계, 제작하였으며 제작된 캐패시터 신뢰성을 검토하였다. 고압용 캐패시터 설계시 절연파괴전압과 유전체 두께간의 최적의 두께가 있음을 볼 수 있으며 그린시트 두께 24 um의 경우 weibull 계수는 13.38, 단위 절연파괴전압은 70 [V/um]을 얻을 수 있었다. X7R 3216, 100 [nF] 정격전압 250[V] 캐패시터를 설계하여 절연파괴전압은 최고 1.29 [KV]인 고압용 칩 캐패시터를 제작하였다. 적층 칩 캐패시터 절연파괴 모드는 유전체 층간의 절연파괴와 더불어 내부전극과 외부 전극 또는 세라믹 소체와의 절연파괴 모드가 나타남을 볼 수 있다.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.71-77
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• 2011

Main parameters of the screen printing were determined and the printing parameters were optimized for 0402, 0603, and 1005 chips in this study. The solder pastes used in this study were Sn-3.0Ag-0.5Cu and Sn-0.7Cu. The process parameters were stencil thickness, squeegee angle, printing speed, stencil separating speed and gap between stencil and PCB. The printing pressure was fixed at 2 $kgf/cm^2$. From ANOVA results, the stencil thickness and the squeegee angle were determined to be main parameters for the printing efficiency. The printing efficiency was optimized with varying two main parameters, the stencil thickness and the squeegee angle. The printing efficiency increased as the squeegee angle was lowered under 45o for all chips. For the 0402 and the 0603 chips, the printing efficiency increased as the stencil thickness decreased. On the other hand, for the 1005 chip, the printing efficiency increased as the stencil thickness increased.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.1
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• pp.32-38
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• 2005

Generally, cutting force models use a sin function method to calculate chip thickness. In slot end milling, the error from a sin function method is much bigger than other machining because a tool rotation angle in cutting is much larger. Thus in this paper, a new method to calculate chip thickness was suggested and evaluated. In a new method, tool position data according to tool rotation are checked and stored so that it is possible correct chip thickness is calculated. Cutting force waveforms simulated from a sin function method and a new method and measured waveforms from experiments were compared and error percentages were obtained. Finally, a new method had good results for simulating cutting force in slot end milling.

• Proceedings of the KAIS Fall Conference
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• 2001.05a
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• pp.148-150
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• 2001

본 논문에서는 소결 후 20 ㎛ 정도의 두께를 갖는 ceramic green sheet를 이용하여 초소형(1005) 칩 인덕터를 제작하였다. 인덕터의 패턴을 최적화함에 있어서 HP사의 HFSS(High Frequency Structure Simulator)를 이용하였고 이 과정에서 인덕터의 전기적 특성, 등가회로등을 추출하였다. 칩 인덕터를 제작함에 있어서 모든 적층 공정을 최적화하였다. 실제 제작한 인덕터와 simulation 결과의 관계성을 도출하고 이를 통해 목표 용량을 tuning하였다. 이와 같은 과정을 통해 1-39 nH의 인덕턴스를 갖는 1005크기의 칩 인덕터를 개발하였고, 이를 선진사의 제품과 비교할 때 우수한 전기적 특성을 나타내었다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.186-186
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• 2011

최근 전자제품의 소형화로 인해 패키징 방법 또한 고밀도 실장법이 연구되고 있다. 고밀도실장을 위해 칩과 솔더간의 간격이 줄어들고, 칩의 두께 또한 얇아지고 있다. 칩과 회로간 연결 소재로는 주석 계열 솔더가 사용 중인데, 고밀도 실장을 위해 산업계에서는 미세 피치에 적합한 솔더를 이용하고 있다. 이에 대한 기초 연구로 순도가 높은 Sn의 wetting 및 기초 솔더링 특성을 평가하였다. 솔더의 spreading, wetting 시험을 실시하였으며, EDS 및 EPMA의 성분분석 평가도 실시하였다.