• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• The Journal of the Korea Contents Association
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• v.9 no.11
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• pp.74-79
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• 2009

This paper proposes a hardware structure and associated finite state machine designs sharing key scheduling circuitry to enhance the performance of the block cypher algorithm, HIGHT. It also introduces an efficient protocol applicable to RFID systems comprising the HIGHT block cipher algorithm. The new HIGHT structure occupies an area size small enough to accommodate tag applications. The structure yields twice higher performance them conventional HIGHT algorithms. The proposed protocol overcomes the security vulnerability of RFID tags and thereby strengthens the security of personal information.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.545-550
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• 2018

Ultra-lightweight block cipher CHAM, consisting of simple addition, rotation, and eXclusive-or operations, enables the efficient implementations over both low-end and high-end Internet of Things (IoT) platforms. In particular, the CHAM block cipher targets the enhanced computational performance for the low-end IoT platforms. In this paper, we introduce the efficient implementation techniques to minimize the memory consumption and optimize the execution timing over 8-bit AVR IoT platforms. To achieve the higher performance, we exploit the partly iterated expression and arrange the memory alignment. Furthermore, we exploit the optimal number of register and data update. Finally, we achieve the high RANK parameters including 29.9, 18.0, and 13.4 for CHAM 64/128, 128/128, and 128/256, respectively. These are the best implementation results in existing block ciphers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.485-494
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• 2012

The block cipher HIGHT is designed suitable for low-resource hardware implementation. It established as the TTA standard and ISO/IEC 18033-3 standard. In this paper, we propose a differentail fault attack against the block cipher HIGHT. In the proposed attack, we assume that an attacker is possible to inject a random byte fault in the input value of the 28-th round. This attack can recover the secret key by using the differential property between the original ciphertext and fault cipher text pairs. Using 7 and 12 error, our attack recover secret key within a few second with success probability 87% and 51%, respectively.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.5
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• pp.107-112
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• 2020

Ultra-lightweight password CHAM is an algorithm with efficient addition, rotation and XOR operations on resource constrained devices. CHAM shows high computational performance, especially on IoT platforms. However, lightweight block encryption algorithms used on the Internet of Things may be vulnerable to side channel analysis. In this paper, we demonstrate the vulnerability to side channel attack by attempting a first power analysis attack against CHAM. In addition, a safe algorithm was proposed and implemented by applying a masking technique to safely defend the attack. This implementation implements an efficient and secure CHAM block cipher using the instruction set of an 8-bit AVR processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.151-153
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• 2016

80/128-비트 마스터키 길이와 ECB, CBC, OFB, CTR의 4가지 운영모드를 지원하는 PRESENT 경량 블록암호 프로세서를 설계하고, Virtex5 FPGA에 구현하여 정상 동작함을 확인하였다. PRESENT 크립토 프로세서를 $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 8,237 GE로 구현되었으며, 최대 434 MHz 클록으로 동작하여 868 Mbps의 성능을 갖는 것으로 예측되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.449-452
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• 2019

초 경량암호 CHAM은 자원이 제한된 장치 상에서 효율성이 뛰어난 덧셈, 회전연산, 그리고 XOR 연산으로 이루어진 알고리즘이다. CHAM은 특히 사물인터넷 플랫폼에서 높은 연산 성능을 보인다. 하지만 사물 인터넷 상에서 사용되는 경량 블록 암호화 알고리즘은 부채널 분석에 취약할 수 있다. 본 논문에서는 CHAM에 대한 1차 전력 분석 공격을 시도하여 부채널 공격에 대한 취약성을 증명한다. 이와 더불어 해당 공격을 안전하게 방어할 수 있도록 마스킹 기법을 적용하여 안전한 알고리즘을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.64-67
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• 2011

최근 개인 프라이버시 보호에 대한 중요성이 제기되면서, 보안에 대한 관심이 증가하게 되었다. 본 논문에서는 한국 산업규격 KS 표준 블록 암호 알고리즘인 ARIA의 핵심논리를 유지하면서, 동종 경쟁 알고리즘(AES, Camellia 등)과의 차별성으로 강조되어온 16 ${\times}16$ 이진 행렬을 이용한 확산 계층을$ (4{\times}4){\times}4$의 이진 행렬 형태로 수정한 개선 ARIA를 구현하였다. 개선 설계된 ARIA를 검증하기 위해, 파일 암.복호화 시스템을 적용하였고, 보안 영상 시스템을 개발하였다. 기존의 ARIA의 장점을 유지하기 때문에, 초경량 환경이나 많은 데이터를 초고속으로 처리에 필요한 응용에 더 효과적으로 적용될 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.