• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.30 no.3
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• pp.12-20
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• 2012

This study was carried out to investigate the backgrounds and spatial characteristics of the sericulture in the rear garden of the palace in Joseon Dynasty. Joseon Dynasty made the various efforts not only to enhance the promotion of agriculture but also sericulture since the main industry of Joseon Dynasty was farming. At the very beginning, Joseon Dynasty planted mulberry trees and built a silkworm-raising room(蠶室) around the Donggung(東宮). Then, King Sungjong(成宗) made Chaesangdan(採桑壇) in Changgyeong Palace and performed Chinzamryae(親蠶禮). The location of Chaesangdan varied as time goes on until the king Gwanghaegun(光海君). Lastly, King Yeongjo(英祖) made Chaesangdan and Junghaechinzambi(丁亥親蠶碑) in Gyeongbok Palace. Yeongjo(英祖) showed a strong attachment to Gyeongbok Palace and actively encouraged the sericulture. Chaesangdan was built in the east side of the palace which was appropriate for planting mulberry trees. Furthermore, a silkworm-raising room was located in this place at the era of King Sejong(世宗).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.48-53
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• 2006

This paper describes the electrical characteristics of monolithic optical transceiver circuitry being used in the fiber optic modules. It has been designed and fabricated, and compared with two chips version transceiver when operates at 155.52 Mbps data rates. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. To compare the two kind of fiber optic modules using each chip, single chip version has similar properties to two chip version in the electrical characteristics as noise and others.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.56-61
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• 2011

This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.32-38
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• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.57-63
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• 2016

This paper describes implementation of the RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4g SUN sensor node transceiver modules. Design of the each module like VCO, prescaler, 1/N divider, ${\Delta}-{\Sigma}$ modulator, and common circuits of the PLL has been optimized to obtain high speed and low noise performance. Especially, the VCO has been designed with NP core structure and 13 steps cap-bank to get high speed, low noise, and wide band tuning range. The output frequencies of the implemented synthesizer is 1483MHz~2017MHz, the phase noise of the synthesizer is -98.63dBc/Hz at 100KHz offset and -122.05dBc/Hz at 1MHz offset.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.8
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• pp.597-609
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• 2020

These days, the coaxial rotor system is used for various purposes like UAVs, Mars exploration helicopters, and the next-generation high-speed rotorcraft. A number of research projects on aerodynamic performance of rotor systems, including the coaxial configuration have been made previously. On the contrary, research on rotor blade deformation has been mainly carried out regarding the single rotor system, where such effort has not been enough on the coaxial system. Nonetheless, in case of the coaxial system, blade deformation analysis is much more important because of the complex air flow around the rotors, and that the distance between the two rotors is a key factor affects aerodynamic performance of the entire system. For these reasons, an experimental study on rotor blade deformation of the coaxial system was conducted using the Stereo Pattern Recognition(SPR) technique, one of the state-of-the-art of photogrammetry method. In this research, a small-scale coaxial rotor test stand designed by Korea Aerospace Research Institute(KARI) was used. With the same test stand, performance of the coaxial configuration had been studied before the experimental study on blade deformation, in order to find the relation between performance and blade deformation of the rotor system. Results of the performance test and the deformation study are presented in this article.

• Korean Journal of Soil Science and Fertilizer
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• v.7 no.1
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• pp.29-34
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• 1974

On a newly reclamed acidic Song-jong soil (soil of a member of fine loamy, mesic family of Hapludults) an experiment was carried out to find out the proper measure of the improvement of soil fertility with soybean as test crop. Results are summarized as follow: 1. Application of compost (1 ton/10a), lime (lime requirement)and fused phosphate (equivalent to 5% of the phosphate fixation coefficient)resulted in the increase of soybean yield by 93.3% over the check plot (N: 6kg/10a, $P_2O_5$: 9kg/10a, $K_2O$: 6kg/10a). The application of fused phosphate at the level of 5% of phosphate fixation coefficient N (6kg/10a) and K(6kg/10a) brought the yield increase by 62.7% over the check plot. However, although the pH of the soil was adjusted to 7.0 by liming, the application of lime with moderate dose of phosphate ($P_2O_5$: 9kg/10a) did not increase the yield of soybean significantly. And the application of fused phosphate at the level of 5% of phosphate fixation coefficient increased the available soil P from 14 ppm to around 100 ppm as tested after harvest. 2. Application of compost (1 ton/10a) increased the organic matter content of soil by 0.8% when tested after harvest. While, the application of rice straw (0.5 ton/10a) did not alter the soil organic matter content. The CEC of the soil tested after havest found incereased significantly by the addition of lime and compost. 3. Plant analysis revealed that the $K_2O/Ca+Mg$ is better correlated with the yield than the absolute concentration of $K_2O$ in plant tissue. Between the concentration of $P_2O_5$ in plant tissue and the yield of soybean, a typical C-curve relationship was observed, indicating that in this particular soil, phosphate was the primary growth liming factor.