• Title/Summary/Keyword: 채널 시뮬레이터

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Analysis of IEEE 802.11n System adapting SVD-MIMO Method based on Ns(Network simulator)-2 (Ns-2 기반의 SVD-MIMO 방식을 적용한 IEEE 802.11n 시스템 분석)

  • Lee, Yun-Ho;Kim, Joo-Seok;Choi, Jin-Kyu;Kim, Kyung-Seok
    • Journal of Korea Multimedia Society
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    • v.12 no.8
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    • pp.1109-1119
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    • 2009
  • WLAN(Wireless Local Area Network) standard is currently developing with increased wireless internet demand. Though existing IEEE 802.11e demonstrates that data rates exceed 54Mbps with assuring QoS(Quality of Service), wireless internet users can't be satisfied with real communication system. After IEEE 802.11e system, Study trends of IEEE 802.11n show two aspects, enhanced system throughput using aggregation among packets in MAC (Medium Access Control) layer, and better data rates adapting MIMO(Multiple-Input Multiple-Output) in PHY(Physical) layer. But, no one demonstrates IEEE 802.11n system performance results considering MAC and PHY connection. Therefore, this paper adapts MIMO in PHY layer for IEEE 802.11n system based on A-MPDU(Aggregation-MAC Protocol Data Unit) method in MAC layer considering MAC and PHY connection. SVD(Singular Value Decomposition) method with WLAN MIMO TGn Channel is used to analyze MIMO. Consequently, Simulation results show enhanced throughput and data rates compared to existing system. Also, We use Ns-2(Network Simulator-2) considering MAC and PHY connection for reality.

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Performance Evaluation of WiBro System based on AMC and H-ARQ by Simulation (AMC와 H-ARQ 에 따른 시뮬레이션 기반의 WiBro 시스템 성능 평가)

  • Seo, Won-Kyeong;Choi, Jae-In;Cho, You-Ze
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1A
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    • pp.19-27
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    • 2011
  • WiBro is a wireless mobile communication system which supports a high data rate and high mobility in anywhere and anytime. Although WiBro system provides multimedia service including data, audio and video services, customers require better service quality in WiBro system. But, many researches have theoretically evaluated the performance of WiBro system without systematic studies by simulation. Therefore, in this paper, we evaluate a performance of WiBro system using OPNET simulator. We analyze system performance according to various modulation and coding schemes, and propose Adaptive Modulation and Coding (AMC) profile to support quality of services for user requirements. Also we evaluate the performance of WiBro system using AMC and Hybrid-Automatic Repeat Request (H-ARQ) technologies, and confirm that the proposed AMC profile can be applied to WiBro system with high performance.

Design of ${\gamma}$=1/3, K=9 Convolutional Codec Using Viterbi Algorithm (비터비 알고리즘을 이용한 r=1/3, K=9 콘벌루션 복부호기의 설계)

  • 송문규;원희선;박주연
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7B
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    • pp.1393-1399
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    • 1999
  • In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

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Simulator Design and Performance Analysis of Link-K Based Relative Navigation System (한국형전술데이터링크(Link-K) 기반 상대항법 시스템의 시뮬레이터 설계 및 성능분석)

  • Lee, Ju Hyun;Lee, Jin Hyuk;Choi, Heon Ho;Choi, Hyogi;Park, Chansik;Lee, Sang Jeong;Lee, Seung Chan
    • Journal of Advanced Navigation Technology
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    • v.20 no.6
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    • pp.528-538
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    • 2016
  • In this paper, an extend kalman filter based relative navigation algorithm is proposed for Link-K based relative navigation. Link-K is a tactical data link system for joint operation capability upgrade of ROK forces. Link-K is inter-operable with Link-16 and transmit and received information of operations and target. In Link-K communication channel, PPLI message including transmitter position and TOA measurement can be used for relative navigation. Therefore Link-K based relative navigation system can be operated. In this paper, software based simulations were carried out for operational feasibility test and performance verification as error factors of proposed Link-K based relative navigation system.

Anti-Spoofing Method Using Double Peak Detection in the Two-Dimensional C/A Code Search Space (이차원 C/A 코드 검색 공간에서의 이중피크 검출을 이용한 기만신호 대응 기법)

  • Kwon, Keum-Cheol;Yang, Cheol-Kwan;Shim, Duk-Sun
    • Journal of Advanced Navigation Technology
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    • v.17 no.2
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    • pp.157-164
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    • 2013
  • In the presence of spoofing signal the GPS signal having the same PRN with the spoofer is hard to be acquired since the power of spoofing signal is usually stronger than that of GPS signal. If a spoofing signal exists for the same PRN, there are double peaks in two-dimensional space of frequency and code phase in acquisition stage. Using double peak information it is possible to detect spoofing signal and acquire GPS information through separate channel tracking. In this paper we introduce an anti-spoofing method using double peak detection, and thus can acquire GPS navigation data after two-channel tracking for the same PRN as the spoofing signal.

Performance evaluation of BWA protocol according to uplink frame size and contention slot (상향링크의 프레임 크기와 경쟁슬롯에 따른 BWA 프로토콜의 성능평가)

  • Oh Sung-Min;Kim Jae-Hyun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11B
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    • pp.967-973
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    • 2004
  • DOCSIS and IEEE 802.16 define the usage and element of a MAP which is uplink control message. Standards does not include the details of MAP size and the number of contention slots affecting the performance of MAC protocols for DOCSIS and IEEE 802.16. In this paper, we analyzed the performance of throughput and access delay according to the MAP size and contention slot size. Based on the analytical results, we found the optimal MAP size and the number of contention slots. We found that the protocol shows best performance when the MAP size is 2msec and the number of contention slots is 8. The simulation results can apply to the network system parameters. The simulator can be used to optimize the system parameters in cable network, BWA and WiBro.

High Breakdown-Voltage AlGaN/GaN High Electron Mobility Transistor having a Trapezoidal Gate Structure (사다리꼴 게이트 구조를 갖는 고내압 AlGaN/GaN HEMT)

  • Kim, Jae-Moo;Kim, Su-Jin;Kim, Dong-Ho;Jung, Kang-MIn;Choi, Hong-Goo;Hahn, Cheol-Koo;Kim, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.10-14
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    • 2009
  • We propose a trapezoidal gate AlGaN/GaN high electron mobility transistor(HEMT) to improve the breakdown voltage characteristics and its feasibility is investigated by two-dimensional device simulations. The use of a trapezoidal gate structure appears to be quite effective in dispersing the electric fields concentrated near the gate edge on the drain side from the simulation result. We find that a peak value of the electric field along the 2-DEG channel is reduced by 30%, from 4.8 to 3.5 MV/cm and thereby, the breakdown voltage(Vbr) of the proposed AlGaN/GaN HEMT is increased by about 40%, from 49 to 69 V, compared to those of the standard AlGaN/GaN HEMT.

Influence of Parasitic Resistances and Transistor Asymmetries on Read Operation of High-Resistor SRAM Cells (기생저항 및 트랜지스터 비대칭이 고저항 SRAM 셀의 읽기동작에 미치는 영향)

  • Choi, Jin-Young;Choi, Won-Sang
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.11-18
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    • 1997
  • By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.

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The hysteresis characteristic of Feedback field-effect transistors with fluctuation of gate oxide and metal gate (게이트 절연막과 게이트 전극물질의 변화에 따른 피드백 전계효과 트랜지스터의 히스테리시스 특성 확인)

  • Lee, Kyungsoo;Woo, Sola;Cho, Jinsun;Kang, Hyungu;Kim, Sangsig
    • Journal of IKEEE
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    • v.22 no.2
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    • pp.488-490
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    • 2018
  • In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characterisitcs, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. To demonstrate the changing characteristics of hysteresis, one of the important features of the feedback field effect transistor, we simulated changing the gate insulating material and the gate metal electrode. The fluctuation in the characteristics changed the $V_{TH}$ of the hysteresis and showed a decrease in width of the hysteresis.

A Hardware-Software Co-verification Methodology for cdma2000 1x Compliant Mobile Station Modem (cdma2000 1x 이동국 모뎀을 위한 하드웨어-소프트웨어 동시 검증 방법)

  • Han, Tae-Hee;Han, Sung-Chul;Han, Dong-Ku;Kim, Sung-Ryong;Han, Geum-Goo;Hwang, Suk-Min;Kim, Kyung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.46-56
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    • 2002
  • In this paper, we describe a hardware-software co-verification methodology and environment in developing a mobile station modem chip for cdma2000 1x which is one of the 3rd generation mobile communication standards. By constructing an efficient co-verification environment for a register-transfer-level hardware model and a physical-layer software model combining a channel link simulator and a versatile test-bench, we can drastically reduce both time and cost for developing a complex three-million-gate class system integrated circuit.