• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.761-768
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• 2017

In this paper, to implement the electromagnetic wave environment and solve electromagnetic compatibility(EMC) problem, miniaturization of ultra-wide band log periodic dipole antenna for measurement was investigated. In addition, in oder to improve the signal-to-noise ratio in high frequency band, balun was connected to the antenna to stabilize the operation of the differential mode antenna and the single mode coaxial cable. To minimize the total size and to increase bandwidth of the antenna, a fat dipole structure was used for the resonance frequency band below 4 GHz and a general dipole shape was used for that above 4 GHz. The bandwidth of the proposed antenna was represented from 0.6 GHz to 8.0 GHz with a ratio bandwidth of 12.3 : 1. Measured peak gain varies from 5.7 dBi to 9.1 dBi, and a half power beamwidth was presented from $29.4^{\circ}$ to $100.2^{\circ}$ in operating range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.73-81
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• 2012

In this paper, we propose a high-speed synchronization method for Digital Radio Mondiale (DRM) receivers. In order to satisfy the high-speed synchronization requirement of DRM receivers, the proposed method eliminate the initial sampling frequency synchronization process in conventional synchronization methods. In the proposed method, sampling frequency tracking is performed after integer frequency synchronization and frame synchronization. Different correlation algorithms are applied to detect the first frame of the Orthogonal Frequency Division Multiplexing (OFDM) demodulation symbol with sampling frequency offset (SFO). A frame detection algorithm that is robust to SFO is selected based on the performance analysis and simulation. Simulation results show that the proposed method reduces the time spent for initial sampling frequency synchronization even if SFO is present in the DRM signal. In addition, it is verify that inter-cell differential correlation used between reference cells is roubst to the effect of initial SFO.

• Journal of Biomedical Engineering Research
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• v.20 no.2
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• pp.205-212
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• 1999

When we want to observe and record a patient's EEG in an operating room, the operation of electrosurgical unit(ESU) causes undesirable artifacts with high frequency and high voltage. These artifacts make the amplifiers of the conventional EEG system saturated and prevent the system from measuring the EEG signal. This paper describes a high-performance bipolar EEG amplifier for a CSA (compressed spectral array ) system with reduced ESU artifacts. The designed EEG amplifier uses a balanced filter to reduce the ESU artifacts, and isolates the power supply and the signal source of the preamplifier from the ground to cut off the current from the ESU to the amplifier ground. To cancel the common mode noise in high frequency, a high CMRR(common mode rejection ratio) diffferential amplifier is used. Since the developed bipolar EEG amplifier shows high gain, low noise, high CMRR, high input impedance, and low thermal drift, it is possible to observe and record more clean EEG signals in spite of ESU operation. Therefore the amplifier may be applicable to a high-fidelity CSA system.

• Journal of IKEEE
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• v.21 no.3
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• pp.248-251
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• 2017

In this paper, The proposed board is developed by EMI compliant Dash Camera with $360^{\circ}$ omni angle. The proposed board is designed by designing DM and CM input noise reduction circuit and applying active EMI filter coupling circuit. The DM and CM input noise reduction circuit design uses a differential op amp circuit to obtain the DM noise coupled to the input signal via the parasitic capacitance(CP). In order to simplify the circuit by applying the active EMI filter coupling circuit, a noise separator is installed to compensate the noise of the EMI source to compensate the CM and DM active filter simultaneously. In order to evaluate the performance of the board for the proposed EMI response, an authorized accreditation body has confirmed that the electromagnetic certification standard for each frequency band is satisfied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.9
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• pp.939-950
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• 1992

The performance of common spreading code scheme employing multiple-capture receiver is compared to that of transmitter-oriented (T/O) code division multiple access (CDMA) scheme in view of the possibility of collision-free transmissions and the effect of secondary multiple-access interference. For performance comparisons, secondary multiple-access interference is characterized for the common code scheme and the T/O CDMA scheme that assures perfectly collision-free transmissions. Throughput performance is then evaluated for these two schemes with direct-sequence spread-spectrum/differential-phase-shift-keying (DS-SS/DPSK) data modulation and forward-error-control coding (BCH codes) in the presence of an additive white Gaussian noise (AWGN). It is shown that when the number of radios is relatively large, the maximum normalized throughput is greater for the common code scheme than for the T/O CDMA scheme at a moderate signal-to-noise ration(SNR).

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.440-449
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• 2008

In this paper, we propose a 16-QAM carrier recovery loop which is suitable for the implementation of Inmarsat M4 system receiver. Because the frequency offset of ${\pm}924\;Hz$ on signal bandwidth 33.6 kHz is recommended in Inmarsat M4 system specification, carrier recovery loop having stable operation in the channel environment with large relative frequency offset is required. the carrier recovery loop which adopts only PLL can't be stable in relatively large frequency offset environment. Therefore, we propose a carrier recovery loop which has stable operation in large relative frequency offset environment for Inmarsat M4 system. The proposed carrier recovery loop employed differential filter-based noncoherent UW detector which is robust to frequency offset, CP-AFC for initial frequency offset acquisition using UW signal, and 16-QAM DD-PLL for phase tracking using data signal to overcome large relative frequency offset and achieve stable carrier recovery performance. Simulation results show that the proposed carrier recovery loop has stable operation and satisfactory performance in large relative frequency offset environment for Inmarsat M4 system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.