• Title/Summary/Keyword: 직류 이득

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A Voltage Disturbance Detection Method for Computer Application Lods (컴퓨터 응용 부하들을 위한 전압 외란 검출 방법)

  • 이상훈;최재호
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.6
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    • pp.584-591
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    • 2000
  • Power Quality Compensator(PQC) has been installed to protect the sensitive loads against the voltage disturbances, such as voltage sag and interruption. In general, static switch is used for the purpose of link between utility and PQC. So transfer operation of the static switch play a important part in the PQC. Many studies on the structure and control of PQC have been progressed in active, but these researches have been rarely mentioned about any voltage-disturbances-detection method to start the PQC operation. In this paper, a new voltage-disturbances-detection algorithm for computer application loads using the CBEMA/ITIC curve is proposed for transfer operation of the static switch. The proposed detection algorithm is implemented to get fast detecting time through the comparison of instantaneous 3-phase voltage values transferred to DC values in the synchronous reference frame with the operating reference values. To get the robust characteristics against the noise, a first order digital filter is designed. The magnitude falling and phase delay caused by the filter are compensated through the error normalizing and numerical analysis using transfer function, respectively. Finally, the validity of the proposed algorithm is proved by ACSL simulation and experimental results.

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Design of Reconfigurable Dual Polarization Patch Array Antenna (재구성 이중편파 패치 배열 안테나 설계)

  • Won Jun Lee;Young Jik Cha
    • Journal of Advanced Navigation Technology
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    • v.27 no.4
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    • pp.463-468
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    • 2023
  • In this paper, we proposed reconfigurable dual polarization patch array antenna that can select two polarizations(Vertical, RHCP) using defected ground structure and Pin diode. The proposed antenna was designed arranging a circular polarization patch antenna implemented with a square microstrip patch and two slots 3x3 at 25.8mm placed, a half-wavelength of 5.8 GHz. Conect the pin diode and the capacitor to the slot diagonally placed on the ground of each antennas, and select polarization using the open/short operating according to the application of DC voltage to the pin diode. As a result of the design, the gain of the antenna is 11.7 dBi at vertical polarization and 11.6 dBic at RHCP. The axial ratio is 20.3 dB at 1.8 dB vertical polarization at RHCP. Mutual Coupling is Maximum to -20.8 dB for vertical polarization and Maximum to -30.1 dB for RHCP.

Design and Experiment of Ku_band Linear Active Phased Array Antenna System (Ku 대역 선형 능동 위상 배열 안테나 시스템 설계 및 실험)

  • Ryu Sung-Wook;Eom Soon-Young;Yun Jae-Hoon;Jeon Soon-Ick;Kim Nam
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.7 s.110
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    • pp.694-705
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    • 2006
  • In this paper, the linear active phased array antenna system operated in Ku DBS band was designed and experimented. The antenna system was composed of sixteen radiating active channels and Wilkinson power combiners with 16-channel inputs, a stabilizing DC bias and phase control board. Electrical beams of the antenna system can be formed by controling the phase-states of 3-bit digital phase shifter inside each active channel by virtue of the phase control board. The amplitude and phase deviations measured between active channels were less than ${\pm}0.8dB$ and ${\pm}15^{\circ}$, respectively, and the noise figure of each active channel was measured less than 1.2 dB in the operating band. The measured performances of the overall antenna system showed the antenna gain of more than 23.07 dBi and the sidelobe level of less than -11.17 dBc, and the bore-sight cross-polarization level of less than -12.75 dBc in the operating band. Also, by phase-controlling active channels, the beam scan patterns at $10^{\circ},\;20^{\circ},\;30^{\circ}$ were measured, and the losses caused by the corresponding beam scanning were 1.1 dB, 2.5 dB and 3.6 dB from the measurements, respectively.

Implementation of Analog Signal Processing ASIC for Vibratory Angular Velocity Detection Sensor (진동형 각속도 검출 센서를 위한 애널로그 신호처리 ASIC의 구현)

  • 김청월;이병렬;이상우;최준혁
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.4
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    • pp.65-73
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    • 2003
  • This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

A Study on the Ultra Small Size 25 Watt High Power Amplifier for Satellite Mobile Communications System at L-Band (L-band 위성통신 시스템을 위한 극소형 25 Watt 고출력증폭기에 관한 연구)

  • Jeon, Joong-Sung;Ye, Byeong-Duck;Kim, Dong-Il
    • Journal of Navigation and Port Research
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    • v.26 no.1
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    • pp.22-27
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    • 2002
  • The 25 Watt hybrid MIC SSPA has been developed in the frequency rang from 1.6265 GHz to 1.6465 GHz for uplink of INMARST's earth station. To simplify the fabrication process, the whole system is designed of two parts composed of a friving amplifier and a power amplifier. The Motorolas MRF-6401 is used for driving part, the Motorolas MRF-16006 and MRF-16030 is used the power amplifier. We reduced weight and volume of high power amplifier through arranging the bias circuits in the same housing. The realized SSPA has more than 30 dB for gain within 20 MHz bandwidth, and the voltage standing wave ratios(VSWR) of input and output port are less than 1.7, respectively. The output power of 44 dBm is achieved at the 1 dB gain compression point of 106365 GHz These results reveal a high power amplifier of 25 Watt which is the design target. The Proposed SSPA manufacture techniques in this paper can be applied to the implementation of high power amplifiers for some radars and SCPC.

Manchester coding of compressed binary clusters for reducing IoT healthcare device's digital data transfer time (IoT기반 헬스케어 의료기기의 디지털 데이터 전송시간 감소를 위한 압축 바이너리 클러스터의 맨체스터 코딩 전송)

  • Kim, Jung-Hoon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.8 no.6
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    • pp.460-469
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    • 2015
  • This study's aim is for reducing big data transfer time of IoT healthcare devices by modulating digital bits into Manchester code including zero-voltage idle as information for secondary compressed binary cluster's compartment after two step compression of compressing binary data into primary and secondary binary compressed clusters for each binary clusters having compression benefit of 1 bit or 2 bits. Also this study proposed that as department information of compressed binary clusters, inserting idle signal into Manchester code will have benefit of reducing transfer time in case of compressing binary cluster into secondary compressed binary cluster by 2 bits, because in spite of cost of 1 clock idle, another 1 bit benefit can play a role of reducing 1 clock transfer time. Idle signal is also never consecutive because the signal is for compartment information between two adjacent secondary compressed binary cluster. Voltage transition on basic rule of Manchester code is remaining while inserting idle signal, so DC balance can be guaranteed. This study's simulation result said that even compressed binary data by another compression algorithms could be transferred faster by as much as about 12.6 percents if using this method.