• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.4
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• pp.28-35
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• 1997

본 논문에서는 송전선로에 직렬로 삽입되어 선로의 리액턴스를 동적으로 보상하는 인버터식 직렬보상기에 대한 동적 응동 해석을 기술하고 있다. 이 직렬보상기는 다중펄스로 동작하는 전압원인버터와 결합변압기, 그리고 제어장치로 구성되어 있으며, 점호각을 조절하여 선로의 리액턴스를 가변하고 용량성 뿐만 아니라 유도성 보상도 가능하다. 이 보상기로 선로의 리액턴스를 감소시키면 전송 유효전력의 증각가 가능한데, 이러한 효과를 본 논문에서는 단일기-무한대-버스 전력계통에 대해 EMTP를 이용한 시뮬레션으로 확인하였으며, 또한 축소모형 제작과 실험을 통해 실험적으로 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.39-45
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• 2004

This paper describes the design and implementation of Serial ATA physical layer and performance measurement. It is composed of tranceiver circuit that has the NRZ data stream with +/-250㎷ voltage level and 1.5Gbps data rate, transmission PLL circuit, clock ＆ data recovery circuit, serializer/deserializer circuit and OOB(Out Of Band) generation/detection circuit. We implement the verification of the silicon chip with 0.18${\mu}{\textrm}{m}$ Standard CMOS process. It can be seen that all of the blocks operate with no errors but the data transfer rate is limited to the 1.28Gbps even this should support 1.5Gbps data transfer rate.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.3
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• pp.11-17
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• 2003

In this paper, we implemented 2-wire (data gnd) RS232C serial communication interface by applying the Collision Sensing Multiple Access(CSMA) Protocol. The transmitting and receiving wires of RS232C pert are connected together by the interface circuit forming data wire without hardware modification On two-wired common channel connection simultaneous transmission Don mere than two hosts causes data collision. The collision is detected by loop-back test of transmission data comparing with the fed back data to detect the data distortion. Various models are adopted to reduce the probability of retransmitted data collision and experiments show the performance of each cases. Due to allowing multiple hosts to be accessed through the common communication channel with minimum circuit addition the result of this paper can be easily applied for conventional RS232C instruments and machines to connect to the single data communication line.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.317-324
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• 2008

In this paper, we propose a system which easily controls the existing serially connected multi-channel speakers in a general personal computer by using a USB(Universal Serial Bus) interface. The personal computer as a host of the USB interface analyzes a sound source and sends audio data in a real-time fashion by the use of the isochronous transmission, one of four transmission methods provided by the USB interface. In addition, a channel is assigned by means of the bulk transmission, one of four transmission methods provided by the USB interface. Transmitted data from the USB host are sent to each speaker through compression and packet generation process. Each speaker detects corresponding digital data and regenerates audio signals through DAC(Digital-to-Analog Converter). A user can easily select a sound source file and a channel by the use of a GUI environment in a personal computer.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.85-92
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• 2000

In this paepr, a multicode CDMA scheme with serial and parallel structure as the transmission scheme of wireless LAN which can transmit high speed data under an indoor channel environment is modeled and optimal values of several parameters needed for implementing wireless LAN modern system are derived through computer simulation. it is verified that given the transmission bandwidth and maximum data rate, the system performance is improved if increasing spreading gain anf the number of channels or decreasing the data rate of each channel. Especially the parallel structure makes not only the system performance much more improved but also the hardware implementation easier than serial structure under the same condition because the effective chip rate is decreased.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.494-503
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• 2003

The IEEE 1394 High Speed Serial Bus is a versatile, high-performance, and low-cost method of promoting interoperability between all types of A/V and computing devices. IEEE 1394 provides two transfer modes: asynchronous mode for best effort service and isochronous mode for best effort service with bandwidth reservation. This paper shows the bus performance and compared the transfer odes first at the link level and then at the application level. For the application level performance, we analyze the bus systems with fixed and adaptive interfaces, applied between the upper layer and the 1394 layer, using polling systems. Also we verifies the analysis models with simulation studies. Based on our analysis, we conclude that the adaptive interface reduces the bus access time and so increases the bus utilization.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.251-255
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• 2015

In this paper, we propose a fuse controller which is used for storing the optimal value or the correction value for the surrounding product of the IoT applications and it is implemented serial communication circuit using a single pin. Because of the proposed single pin protocol is simpler in the hardware than the conventional $I^2C$ and SPI using two or more pins, it is suitable for the area of small amount of data transmission. The function of the one pin protocol is verified by logic simulation and the FPGA test board and it is fabricated using CMOS 0.35um technology. It is expected to use the IoT product that require the low power consumption and simple hardware.

• Electronics and Telecommunications Trends
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• v.20 no.3 s.93
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• pp.112-121
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• 2005

고속직렬프로토콜의 출현으로 기존의 병렬 인터페이스에서 중요하게 사용되던 파라미터들의 의미가 변화되고 있다. 특히 ‘1’, ‘0’의 디지털 신호가 고속의 차동신호로 전송되면서 신호 무결성의 파라미터로 지터(jitter)가 중요한 의미를 가지게 되었다. 본 고는 지터의 발생과 분석, 테스트 등 전분야를 다루고 있다. 지터를 분석하기 위한 방법으로 Eye Diagram, Bathtub 곡선, TIE 히스토그램 등을 다루며 이러한 방법을 사용하여 지터를 각각의 특성별로 분리한다. 그리고 지터를 테스트 장비와 각각의 특징을 살펴본 후 PCI Express 트랜시버 지터 테스트의 실례를 통하여 지터 테스트 방법과 분석을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.1-10
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• 2001

This paper describes new line code algorithm, called NIDI(Nibble Inversion mock Inversion) which is well suited for interconnection and transmission technology, The proposed line code which includes only one redundancy bit serves primary features of line code and synchronization patterns for byte or frame synchronization in interconnection, Also, this line code provides in-band signals and speciaI characters.