• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• The KIPS Transactions:PartD
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• v.10D no.3
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• pp.439-446
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• 2003

A crucial limitation in environments where data is broadcast to very large client populations is the low bandwidth available for clients to communicate with servers. Many advanced applications are developed in mobile computing environments, but conventional concurrency controls are not suitable because of the low bandwidth of wireless network. In this paper, we propose a new optimistic concurrency control protocol for mobile transactions. In this protocol, mobile read-only transactions can be completed locally at the clients without additional communication, only mobile update transactions are sent to the server for global validation. Our protocol reduces unnecessary aborts occurred in the previous study using only conflict information. In addition to, our algorithm can detect and resolve non-serializable execution using by data table maintained in a server.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.5
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• pp.443-452
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• 2002

A new phase shift full bridge (PSFB) converter with serially connected two transformers for telecommunication equipments of several hundred watts is proposed. The main features of the proposed converter are a wide input voltage range, an easiness to meet the requirement for zero voltage switching (ZVS) condition at a light load, and a small output voltage ripple. Furthermore, the serially connected two transformers can replace both a main transformer and an output inductor since the two transformers act as not only a main transformer but an output inductor by turns. Therefore, there is no need to use an output inductor, then the proposed converter features high power density. A mode analysis, design equations through a large signal modeling, and experimental results are presented to verify the validity of the proposed converter.

• Journal of IKEEE
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• v.26 no.3
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• pp.437-444
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• 2022

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. In automotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatal results may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C, there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in this paper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and the verification is presented by designing it in hardware.

• Journal of Digital Convergence
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• v.12 no.12
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• pp.257-264
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• 2014

Through MCU model, Radio Frequency communication is completed using universal asynchronous receiver and transmitter. The communicatin with PC and MCU is completed using RS-232 cable. At first interconnected communication with PC and MCU is necessary for RF communication because tha UART is based technique for RF communication. Program imbeded in microcontroller unit is ran during RF signal is transmitted to other RF module. Data connected with PC and MCU is transmitted between PC and MCU during PC and MCU is connected.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2245-2251
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• 2013

In this paper, a design of a compact series-fed dipole pair(SDP) antenna with end-loaded rectangular patches is presented. In order to reduce the lateral size of a conventional SDP antenna, rectangular patches are end-loaded to the two dipole elements of the SDP antenna and a grooved ground plane is used by adding a patch at both ends of the ground plane. The effects of varying the length and width of the rectangular patches on the antenna performance such as input reflection coefficient are investigated. An optimized compact SDP antenna covering a frequency band ranging from 1.7 GHz to 2.7 GHz is designed and fabricated on an FR4 substrate. The total width of the fabricated prototype of the proposed antenna is reduced by approximately 14.3% compared to the conventional SDP antenna. Experimental results show that the antenna presents a 48.7% bandwidth in the range of 1.68-2.76 GHz and a stable gain of 5.6-6.0 dBi with minimal degradation. Moreover, a front-to-back ratio is improved by about 0.7 to 7.4 dB.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.190-195
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• 2000

This paper presents the fabrication of the LNA which is operating at 2.13∼2.16 GHz for IMT-2000 lot-end receiver using series feedback and resistive decoupling circuit. Series feedback added to the source lead of a transistor keep the low noise characteristics and drop the input reflection coefficient of amplifier simultaneously. Also, it increases the stability of the LNA. Resistive decoupling circuit is suitable for input stage matching because a signal at low frequency is dissipated by a resistor in the matching network The amplifier consist of GaAs FET ATF-10136 for low noise stage and VNA-25 which is internally matched MMIC for high gain stage. The amplifier is fabricated with both the RF circuits and self bias circuit on the Teflon substrate with 3.5 permittivity. The measured results of the LNA which is fabricated using above design technique are presented more than 30 dB in gain P$\_$ldB/ 17 dB and less than 0.7 dB in noise figure, 1.5 in input$.$output SWR(Standing Wave Ratio).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.471-472
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• 2015

In this paper, a design method for enhancing the gain of a series-fed dipole pair (SDP) antenna using mutiple directors is studied. Strip-type directors are located above the second dipole of the SDP antenna, and the variations of the input VSWR bandwidth and gain depending on the length of the second dipole and the number of directors are analyzed. The antenna is optimized to obtain gain > 8 dBi in the frequency range of 1.7-2.7 GHz, which has three directors in the optimum design. The optimized antenna is designed on an FR4 substrate with a dimension of 86.2 mm by 152.3 mm, and it has frequency bands of 1.67-2.79 GHz for a VSWR < 2 and 1.69-2.72 GHz for a gain > 8 dBi.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.10
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• pp.1855-1861
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• 2017

In this paper, the gain enhancement of an SDPA using a director and two parasitic patches is studied. The modified balun is used to increase the bandwidth, whereas the director and two parasitic patches are appended to the SDPA to enhance the gain in the middle and high frequency bands. The effects of the distance between the director and parasitic patches on the antenna performance are analyzed, and the SDPA with a gain over 7 dBi at 1.54-2.99 GHz band is designed. The proposed SDPA is fabricated on an FR4 substrate with a dimension of $90mm(L){\times}135mm(W)$ in order to validate its performance. The fabricated antenna shows a frequency band of 1.56-3.10 GHz for a VSWR < 2, and it is confirmed by measurement that gain maintains over 7 dBi in the frequency range of 1.54-3.00 GHz.