• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.46-51
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• 2002

A new interleaved synchronous mirror delay(SMD) is proposed in order to reduce the circuit size and the power. The conventional interleaved SMD has multiple pairs of forward delay array(FDA) and backward delay away(BDA) in order to reduce the jitter. The proposed interleaved SMD. requires one FDA and one BDA by changing the position of multiplexer. Moreover, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on a 0.25um two-metal CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.671-672
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• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.63-68
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• 2004

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

• ETRI Journal
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• v.14 no.3
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• pp.75-96
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• 1992

이중 매몰층, $1.5\mum$ 에피두께, 이중 well, LOCOS 소자격리, LDD MOS 소자와 이중 다결정실리콘 전극을 갖는 바이폴라 소자에 의하여 구성된 BiCMOS 소자를 제작하였다. 제작된 소자를 측정 및 분석한 결과, 31단 CML 바이폴라($A_E=2X8\mum^2$)링 발진기와 31단 CMOS( $A_E=1.25X5\mum^2$) 인버터 링 발진기로부터 94ps/5V 와 330ps/12V의 게이트 전달 지연시간/소자 강복전압을 갖는 바이폴라 및 MOS소자특성을 얻을 수 있었다. 또한 BiCMOS 소자의 경우, 31단 BiCMOS 링 발진기로부터 약 700ps의 게이트 전달 지연시간을 얻었으며, 출력부하의 증가에 따른 속도의 감속비가 완만한 전기적 특성을 얻을 수 있었다.

• Korean Journal of Optics and Photonics
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• v.16 no.2
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• pp.133-137
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• 2005

A photonic RF true-time delay using a tapered chirped fiber Bragg grating coated with a heating electrode has been proposed and fabricated. For an RF signal carried over an optical signal, the time delay has been achieved by controlling the voltage applied to the electrode and thus adjusting its reflection positions from the fiber grating through the thermooptic effect. It features continuous voltage-controlled operation, requiring no mechanical perturbation and no moving parts. The measured time delay was about 120 ps with the electrical power consumption of $250{\cal}mW$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.681-689
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• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.236-244
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• 2010

In this paper, a planar structure negative group delay circuit(NGDC) is proposed to overcome the limited availability of the component values required for the prototype lumped element(LE) NGDC design. From the prototype LE circuit analysis, general design equations and the conditions to obtain the NGD are derived and illustrated. Then the LE circuit is converted into the planar structure by applying the transmission line resonator(TLR) theory. As a design example, the LE NGDC and the proposed planar structure NGDC are designed and compared. To estimate the commercial applicability, 2-stage reflection type planar NGDC with -5.6 ns of total group delay, -0.2 dB of insertion loss, and 30 MHz of bandwidth together with 0.1 dB and 0.5 ns of the magnitude and group delay flatness, respectively, for Wideband Code Division Multiple Access(WCDMA) downlink band is fabricated and demonstrated. Also, to show the applicability of the proposed NGDC, we have configured a simple signal cancellation loop and obtained good loop suppression performance.

• The Optical Journal
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• s.122
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• pp.25-27
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• 2009

최근 나노기술이 발전을 거듭하면서 새로운 소자들에 대한 연구개발이 활발히 전개되고 있다. 서울대학교 융합나노소자연구실은 탄소 나노튜브와 실리콘 나노선 등 반도체 및 디스플레이의 첨단산업분야에서 많이 쓰이고 있는 소자들을 결합시켜 새로운 소자를 만들어내는 연구를 진행하고 있다. 특히 나노소자의 대량생산 기술에 관심을 갖고 세계적인 연구개발 업적을 꾸준히 내놓으면서 이 분야에서 독보적인 영역을 구축해 나가고 있다.

• Journal of the Korean Society for Nondestructive Testing
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• v.19 no.3
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• pp.207-216
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• 1999

A phased array is a multi-element piezoelectric device whose elements are individually excited by electric pulses at programmed delay time. One of the advantages of using phased array in nondestructive evaluation (NDE) application over conventional ultrasonic transducers is their great maneuverability of ultrasonic beam. There are some parameters such as the number and the size of the piezoelectric elements and the inter-element spacing of the elements to design phased array transducer. In this study, the characteristic of ultrasonic beam for phased array transducer due to the variation of the number of elements has been simulated for ultrasonic SH-wave on the basis of Huygen's principle. Ultrasonic beam directivity and focusing due to the change of time delay of each element were discussed due to the change of the number of piezoelectric elements. It was found that ultrasonic beam was much more spreaded and hence its sound pressure was decreased as steering angle of ultrasonic beam was increased. In addition, the ability of ultrasonic bean focusing decreased gradually with the increase of focal length at the same piezoelectric elements. However, the ability of beam focusing was improved as the number of consisting elements was increased.

• Korean Journal of Optics and Photonics
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• v.17 no.2
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• pp.159-164
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• 2006

We demonstrate a compact optical coherence tomography(OCT) system based on the optical fiber delay line controlled by a cylindrical piezo-electric transducer(PZT). An 18-m length of single mode fiber is wrapped under constant tension around a PZT. Approximately 134 windings are used. Wraps of the long length of fiber allow the small expansion of the PZT to be magnified to an optical path length delay of 0.78 m. The OCT system shows characteristics for 2-dimensional imaging, exhibiting 96.9dB of signal-to-noise ratio(SNR), $18.6{\pm}0.5\;{\mu}m$ of axial resolution, and $5\;{\mu}m$ of lateral resolution with samples.