• Title/Summary/Keyword: 지연 계산

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Retardation of Mobility of Gaseous VOCs in the Unsaturated Zone (불포화대중 휘발성 유기화합물 가스의 이동지연현상)

  • 이창수;배우근
    • Journal of Korea Soil Environment Society
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    • v.4 no.2
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    • pp.103-111
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    • 1999
  • This study is on the mathematical modeling and its verification of the retardation phenomenon of gas migration in an unsaturated zone of very little moisture content The adsorption of VOCs onto the surface of the dry medium was taken into account, which has not been usually considered in the conventional models. The trichloroethylene(TCE) gas migration predicted from the mathematical model developed in this study fits the experimental results obtained from a dry glass-bead column and a dry silica sand column very well The model developed in this study gave much better prediction than did a coventional model.

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An Improved Timing-level Gate-delay Calculation Algorithm (개선된 타이밍 수준 게이트 지연 계산 알고리즘)

  • Kim, Boo-Sung;Kim, Seok-Yoon
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.8
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    • pp.1-9
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    • 1999
  • Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

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Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes (지연시간과 회로 구조 변화를 고려한 증가적 타이밍 분석)

  • O, Jang-Uk;Han, Chang-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.8
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    • pp.2204-2212
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    • 1999
  • In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

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New Weight Generation Algorithm for Path Delay Fault Test Using BIST (내장된 자체 테스트에서 경로 지연 고장 테스트를 위한 새로운 가중치 계산 알고리듬)

  • Hur, Yun;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.6
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    • pp.72-84
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    • 2000
  • The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.

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Compiling Lazy Functional Programs to Java on the basis of Spineless Taxless G-Machine with Eval-Apply Model (Eval-Apply 모델의 STGM에 기반하여 지연 계산 함수형 프로그램을 자바로 컴파일하는 기법)

  • Nam, Byeong-Gyu;Choi, Kwang-Hoon;Han, Tai-Sook
    • Journal of KIISE:Software and Applications
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    • v.29 no.5
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    • pp.326-335
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    • 2002
  • Recently there have been a number of researches to provide code mobility to lazy functional language (LFL) programs by translating LFL programs to Java programs. These approaches are basically baled on architectural similarities between abstract machines of LFLs and Java. The abstract machines of LFLs and Java programming language, Spineless Tagless G-Machine(STGM) and Java Virtual Machine(JVM) respectively, share important common features such as built- in garbage collector and stack machine architecture. Thus, we can provide code mobility to LFLs by translating LFLs to Java utilizing these common features. In this paper, we propose a new translation scheme which fully utilizes architectural common features between STGM and JVM. By redefining STGM as an eval-apply evaluation model, we have defined a new translation scheme which utilizes Java Virtual Machine Stack for function evaluation and totally eliminates stack simulation which causes array manipulation overhead in Java. Benchmark program translated to Java programs by our translation scheme run faster on JDK 1.3 than those translated by the previous schemes.

A Loop Shaping Method of PID Controller for Time delay Systems (시간 지연이 있는 시스템에서의 PID 제어기 설계를 위한 루프 형성 기법)

  • Yun Seong o;Suh Byung suhl
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.10C
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    • pp.1370-1377
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    • 2004
  • Optimal control gain for time-delay systems is made by an optimal control gain for delay-free systems multiplied by a state transition function for the delay time. The optimal control gain for delay-free systems is obtained by pushing two zeros of the PID controller closely to a larger pole of the second order plant. Thus the optimal tuning of PID controller for time-delay second order system is able to be obtained by calculation for the state transition function.

Parallel Priority Queuing Algorithm for Cell Scheduling In ATM Multiplexers (ATM 다중화기에서 셀 스케쥴링을 위한 병렬 우선순위 큐잉 알고리즘)

  • 유초롱;김미영;권택근
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10c
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    • pp.405-407
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    • 1999
  • WFQ(Weighted Fair Queuing)은 지연이나 공평성의 특성에 있어서 이상적인 트래픽 스케줄링 알고리즘으로 간주되었다. N세션에 서비스를 제공하는 WFQ 스케줄러의 스케줄링 연산은 각 패킷 전송 시간당 O(n)의 계산 복잡도를 가지며, 구현 또한 복잡하다. Self-Clocked Fair Queuing과 같은 WFQ 알고리즘의 구현을 간단히 하고자 하는 노력은 지연범위나 특성에 영향을 주게 되어 다양한 트래픽이 제공되는 경우 각 트래픽의 공평성을 지원해주지 못한다. 그러므로 지연이나 지연 변이 측면에서 공평성을 지원하고 구현상의 계산 복잡도를 줄인 스케줄링 알고리즘이 필요하게 되었다. ATM 다중화기의 셀 스케줄링 알고리즘 역시, ATM의 특성상 다양한 특성의 서비스를 제공하기 위해서, 다양한 특성의 트래픽에 대한 공평성을 제공하는 새로운 알고리즘의 연구가 필요하다. 이 논문에서는 ATM 스위치 내의 다중화기에서 사용되는 새로운 셀 스케줄링 알고리즘을 제안하고 실험을 통해 이 알고리즘의 성능을 검증하고자 한다. 이 알고리즘은 여러 개의 우선 순위 큐를 갖고, 각 우선순위 큐마다 스케줄링 연산이 O(1)의 계산 복잡도를 갖는 Parallel Priority Queuing 알고리즘이다.

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A CMOS Cell Driver Model to Capture the Effects of Coupling Capacitances (결합 커패시턴스의 영향을 고려한 CMOS 셀 구동 모델)

  • Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.41-48
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    • 2005
  • The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.

Per Class Delay Estimation to Guarantee Dynamic Priority for Multimedia Traffic (멀티미디어 트래픽의 동적 우선순위를 보장하기 위한 클래스별 지연 시간 예측 기법)

  • Lee, Dong-Ho;Chung, Kwang-Sue
    • Proceedings of the Korean Information Science Society Conference
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    • 2011.06d
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    • pp.283-286
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    • 2011
  • 무선 멀티홉 네트워크에서 멀티미디어 트래픽의 QoS(Quality of Service) 지원을 위하여 EDCA(Enhanced Distributed Channel Access) 기반의 동적 우선순위 할당 기법이 다수 제안되었다. 해당 기법들은 각 홉에서의 최소한의 전송 지연 보장을 위하여 클래스별 예상 지연 시간을 계산한다. 하지만 각 클래스별 예상 지연 시간의 계산은 무선 채널에서의 간섭, 충돌 및 링크 품질에 영향을 받기 때문에 정확한 예측이 어렵다. 본 논문에서는 EDCA 기반의 동적 우선순위 할당을 위한 정교한 클래스별 지연 시간 예측 기법을 제안한다. 제안하는 기법은 무선 채널의 링크 품질과 전송 패킷의 크기를 고려하여 좀더 실제와 유사한 지연 시간을 예측할 수 있다. 실험을 통해 제안하는 기법이 기존의 기법보다 정확성이 높으며 이를 통해 동적 우선순위 할당 기법의 성능을 향상시킬 수 있음을 확인하였다.

The Real-Time Determination of Ionospheric Delay Scale Factor for Low Earth Orbiting Satellites by using NeQuick G Model (NeQuick G 모델을 이용한 저궤도위성 전리층 지연의 실시간 변환 계수 결정)

  • Kim, Mingyu;Myung, Jaewook;Kim, Jeongrae
    • Journal of Advanced Navigation Technology
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    • v.22 no.4
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    • pp.271-278
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    • 2018
  • For ionospheric correction of low earth orbiter (LEO) satellites using single frequency global navigation satellite system (GNSS) receiver, ionospheric scale factor should be applied to the ground-based ionosphere model. The ionospheric scale factor can be calculated by using a NeQuick model, which provides a three-dimensional ionospheric distribution. In this study, the ionospheric scale factor is calculated by using NeQuick G model during 2015, and it is compared with the scale factor computed from the combination of LEO satellite measurements and international GNSS service (IGS) global ionosphere map (GIM). The accuracy of the ionospheric delay calculated by the NeQuick G model and IGS GIM with NeQuick G scale factor is analyzed. In addition, ionospheric delay errors calculated by the NeQuick G model and IGS GIM with the NeQuick G scale factor are compared. The ionospheric delay error variations along to latitude and solar activity are also analyzed. The mean ionospheric scale factor from the NeQuick G model is 0.269 in 2015. The ionospheric delay error of IGS GIM with NeQuick G scale factor is 23.7% less than that of NeQuick G model.