• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5B
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• pp.270-276
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• 2007

The proposed LDS(Link-status Dependent Scheduling) algorithm in HR-WPAN(High Rate-Wireless Personal Area Network) up to now aims at doing only throughput elevation of the whole network, when the crucial device is connected with worst-link relatively, throughput of this device becomes aggravation. The proposed the WGS(Worst-case Guaranteed Scheduling) algorithm in this paper guarantees throughput of the device which is connected with worst-link in a certain degree as maintaining throughput of all devices identically even if a link-status changes, decreases delay of the whole network more than current LDS algorithm. Therefore proposed WGS algorithm in this paper will be useful in case of guaranteeing throughput of a device which is connected worst-link in a certain degree in a design of HR-WPAN hereafter.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.536-541
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• 2000

Turbo code has excellent decoding performance but had limitations for real time communications because of the system complexity and time delay in decoding procedure. To overcome this problem, a new SRI(Semi-Random Interleaver) algorithm which realize the reduction of the interleaver size is proposed for reducing the time delay during the decoding prodedure. SRI compose the interleaver 0.5 size from the input data sequence. In writing the interleaver, data is recorded by row such as block interleaver. But, in reading, data is read by randomly and the text data is located by the just address simultaneously. Therefore, the processing time of with the preexisting method such as block, helical random interleaver.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.4
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• pp.339-345
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• 2007

This paper presents a design of an FPGA (Field Programmable Gate Array) -based currentcontroller. Using the nature of the high computational capability of FPGA, the digital delay due to the algorithm execution can be reduced. The control performance can be better than the conventional DSP (Digital Signal Processor)-based current controller. Moreover, this method does not need any delay compensation algorithm because the digital delay is physically diminished. Therefore, the bandwidth of the current controller can be extended by this method. The feasibility of this method is verified by several experimental results under the various conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12B
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• pp.1037-1043
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• 2006

There has been proposed an algorithm to reduce data burst processing delay in group scheduling in core nodes of optical burst switching networks. Since, in this algorithm, look-up tables containing all the void time information in scheduling windows are generated as soon as the primary group scheduling session terminates, it becomes faster to reassign dropped data bursts to proper voids in different data channels by referring to the tables. The group scheduling with this algorithm showed almost the same channel utilization as the one without using the algorithm but performed a little better in both burst loss probability and wavelength conversion rate. On the other hand, per-burst processing time has been reduced dramatically in the load region of higher than 0.8, showing a factor of 2.1 reduction at 0.9.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.5
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• pp.115-121
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• 2009

In this paper, we propose an algorithm that reduces channel change delay time in the P2P based IPTV system. Channel change delay time is considered to be one of the most important performance measures in IPTV system. Proposed algorithm presents a method to reduce the channel change delay time effectively. The algorithm eliminates the first channel change delay time and reduces delay time on a continuous channel surfing. We will show the mathematical models to evaluate the performance of proposed scheme with respect to the channel change delay time.

• Journal of Broadcast Engineering
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• v.12 no.1 s.34
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• pp.28-40
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• 2007

In this paper, we proposes an idea for improved sound characteristic which decreasing a problem in previous reverberation algorism structure. To later reflection sound, proposed new reverberation structure, using a lopped and nested all-pass delay line, and it is designed to improve an natural concert hall sound. In addition, In order to have best imaginary sound effect, we extracted the factors by controlling each delay line's delay time, and we realized a proposed new algorithm by using general-purpose DSP. Through several experimental cases, we observed better effect on improvement of linear flatten and reverberation density and decreasing about colorlessness and non-linear sound at previous proposed model about impulse input.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.35-43
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• 2006

In the paper, we propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in Statistical Static Timing Analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of proposed method has been verified on ISCAS85 benchmark circuits with $0.16{\mu}m$ model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.120-122
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• 2015

In this paper, we proposed an algorithm of the unnecessary copied message inhibition using dynamic density what is called DDIM(Dynamic Density-based Inhibited Message diffusion) in DTNs(Delay Tolerant Networks). Existing DTN routing algorithms as Epidemic and Spray and Wait have some problems that occur large overhead in dense network due to the thoughtless message diffusion. Our proposed method, the DDIM, determines adjusted number of copied message through dynamic node density that is calculated using node's radio coverage and neighbor nodes in period time to solve message diffusion problem. It decrease overhead without losing message delivery ratio and increased latency through reducing message diffusion. In this paper, we compare delivery ratio, average latency and overhead of proposed algorithm, DDIM, and existing DTN routing algorithm and prove enhanced performance through simulation results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.10-16
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• 2003

In this paper, a dynamic contention periods based on the collision group(DCCG) algorithm is proposed for collision resolution in the IEEE 802.16 broadband wireless access network. The DCCG algorithm determines the contention periods according to the a number of collided slot and collided requests to the base station(BS). The DCCG algorithm is useful to improve the performance of throughput and system delay characteristic than binary backoff algorithm.