• Title/Summary/Keyword: 지연이자

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자율운항선박 원격제어에서 제어지연의 본선 도메인 침공 연구

  • 임정빈;예병덕
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • 2021.11a
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    • pp.172-173
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    • 2021
  • 자율운항선박의 원격제어에서 제어지연이 발생하면 선박은 충돌위험에 처하게 됨으로 이에 대한 해결방안 필요하다. 연구 목적은 자율운항선박의 원격제어에서 제어지연이 선박충돌에 미치는 영향을 조사하기 위함이다. 연구 방법은, 선박의 터닝서클을 시뮬레이션을 통해서 관측하고, 이 데이터를 이용하여 제어지연에 의한 영향을 분석하였다. 이를 위하여 제어지연(시간)에 따른 선박조종 시뮬레이션의 선회권 측정 데이터를 이용하였다. 연구 결과, 제어지연에 의해서 본선 도메인 침공당하는 방위와 최소거리 분석 가능함을 알았다.

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An Analysis on Work Delaying Factors in Apartment Building Construction (공동주택 공사의 작업지연요소 분석)

  • Ahn, Sang-Hyun;Yu, Jung-Ho;Kim, Chang-Duk
    • Proceedings of the Korean Institute Of Construction Engineering and Management
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    • 2006.11a
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    • pp.496-501
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    • 2006
  • Work delay is the one of facts that make the reliability of construction business decrease. Building a causal classification system of work delay and deducing the managemental item for it gives a great competition to the construction industry. It is, however, so rare to study about work delay so far. Therefore, this research analyzed a questionnaire, which is focussing on the public apartment construction, to look into the causal root factors and deduce the work delay factors. Finally, we suggest a major managing point to remove effectively the work delay factors.

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A Delay Analysis based on the Comparison of the As-planned Schedule, As-built Schedule including All Delays and As-built Schedule absent Owner Delays (계획공정표, 모든 지연을 포함한 준공공정표, 발주자 지연을 제외한 준공공정표의 비교를 통한 공기지연분석)

  • Yun Chul-Sung;Chu Hae-Keum;Kim Seon-Gyoo
    • Proceedings of the Korean Institute Of Construction Engineering and Management
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    • autumn
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    • pp.426-429
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    • 2003
  • In the construction process, there are many change orders differing to the initial contracts came from the social needs and environmental changes. Most of them will impact to the construction process so that its effects occur project delays. Time extension and liquidated damage in the construction process come from schedule delay whether it is excusable or not non-excusable by the owner. However, those become the delay claims if the owner and the contractor are not agreed on this situation. One of the most important thing on the delay claims is the calculation of delay. The purpose of this study is to present the method of the time delay calculation by comparison of As-Planned schedule, As-Built schedule including all delay and As-Built schedule absent owner delay.

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A Study on the Change of Burning Rate of Zirconium-Nickel Delay Elements Depending on the Ambient Temperature (Zr/Ni계 지연제의 주변 온도에 따른 연소속도 변화 연구)

  • Kim, Ho-Sub;Lim, Ho Young;Kang, Yo Han;Kim, Do Hyun;Lee, Geun Woo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.7
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    • pp.82-89
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    • 2020
  • Among the explosives in ammunition, the delay elements, which are used as a retardant, could be influenced by the ambient temperature in the Republic of Korea, where the highest and lowest average annual temperature difference is clear. On the other hand, there has been no domestic research on this. This study examined the linear burning rates of the zirconium-nickel delay elements depending on the ambient temperature in South Korea. The ambient temperature data of South Korea were obtained from the meteorological administration, which was used to set the experimental conditions. The operational time for the K414 fuze was measured by changing the ambient temperature by 10 ℃ from -40 ℃ to 50 ℃. To convert the delay time into the burning rates, the height of the delay element in the K414 fuze body was used. The results indicated that the characteristics of the burning rates for the zirconium-nickel delay element could be estimated as linear, and both the burning rates and the delay time of the zirconium-nickel delay element were 2.73mm/ms and -4.18ms, respectively. This led to an approximately 80 ms delay time difference in the environment where the highest and lowest average annual temperature difference was above 20 ℃. Therefore, the delay time reflecting the ambient temperature should be considered when the test evaluation criteria of zirconium-nickel delay elements are established.

Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes (지연시간과 회로 구조 변화를 고려한 증가적 타이밍 분석)

  • O, Jang-Uk;Han, Chang-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.8
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    • pp.2204-2212
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    • 1999
  • In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

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Type-Based Group Delay Equalizer Considering the Nonlinear Phase Distortion of HPA (HPA의 비선형 위상 왜곡을 고려한 타입기반 군 지연 등화기)

  • Kim, Yongguk;Jo, Byung Gak;Baek, Gwang Hoon;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37A no.10
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    • pp.895-902
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    • 2012
  • In this paper, we propose a novel equalizer to compensate for the group delay including AM/PM nonlinear distortion characteristics by the nonlinear power amplifier (PA). The group delay characteristic is a nonlinear non-constant time delay that appears differently depending on each frequency component. The phase distortion by AM/PM characteristics arising from the power amplifier is a major factor to increase group delay. By the group delay distortion, the signal in the constellation expands and is rotated. Considering the problem mentioned above, the nonlinear time delay that appears differently depending on each frequency component is classified as a static group delay and AM/PM characteristic of PA, the different phase transitions depending on the size of input signal as a dynamic group delay. Static group delay estimates and compensate for phase distortions in the frequency domain with type-based method and dynamic group delay compensates for phase rotation in the time domain. We confirmed that the group delay compensation techniques were enough to compensate the group delay characteristics including AM/PM characteristics of the power amplifier.

The Relationships among Infant's Delay Gratification, Delay Strategy, and Parents' Child-rearing Attitude (영아의 만족지연능력과 만족지연전략 및 어머니의 양육방식간의 관계)

  • Choi, Eun Hwa;Cho, Bok Hee
    • Korean Journal of Childcare and Education
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    • v.1 no.1
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    • pp.167-189
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    • 2005
  • The purpose of this study was to examine the relationships among delay gratification, delay strategy, and parents' child-rearing attitude. The participants of the study were 62, 18-36 month old infants, who demonstrated individual differences in the level of delay gratification and their mothers. The instruments of the study were infant's delay gratification and delay strategy were assessed by Mischele(1974) and the parents' responded to the parents' child-rearing attitude(Cho et al., 1999). Data were collected by menas of conducting observations on infants in experimental settings and completing questionnaires with mothers. The results of this study were as follows: 1. The delay gratification of infants differed accordingly to their age. Older infants displayed increased time in showing their delay gratification, while younger infants relatively exhibited shortened time. There was no significant difference in infants' sex and the order of the birth. 2. Following the age factor, the distraction strategy in the delay strategy played a significant difference to infants. Older infants required a frequent use of the distraction strategy in comparison to younger infants. 3. The previous two factors - delay gratification and distraction strategy-showed a positive relationship. 4. The delay gratification was significantly influenced by infants' age, parents' attitude, direct facing strategy, and infants' distraction strategy. However, the delay gratification was insignificantly accounted for by infants' sex.

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A Output Link Service Algorithm from the Aspects of Delay and Bandwidth Normalization (지연-대역폭 정규화 관점에서의 출력링크 서비스 알고리즘)

  • Lee, Ju-Hyun;Hwang, Ho-Young;Min, Sang-Lyul
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.10d
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    • pp.259-262
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    • 2006
  • 라우터에서 세션간 출력링크 용량을 공정하게 분배하기 위해, Generalized Processor Sharing(GPS) 기반 공정큐잉 알고리즘들이 제안되었다. 이 알고리즘들은 대역폭 관점에서는 서버에 대기중인 각 세션들에게 공정한 서비스를 제공해 주지만, 지연 관점에서는 경계치 이하로 보장해 주는 서비스만 제공한다. 이로 인해 적은 양의 패킷을 생성하는 세션이라도 작은 지연으로 서비스 받고자 한다면, 큰 대역폭을 할당받아야 하는 문제가 발생한다. 이와 같이 지연과 대역폭이 결합됨으로 써 생기는 문제를 해결하고자 서비스커브 기반의 알고리즘이 제안되었지만, 이 알고리즘들은 서비스 지연과 대역폭간 제한된 분리밖에 지원하지 못한다. 본 논문에서는 서비스 지연과 대역폭을 분리하여 독립적으로 처리함으로 써, 각 세션에게 세션의 트래픽 특성에 맞게 서비스를 제공해 주는 지연-대역폭 정규화 모델을 제안한다. 이 모델은 서비스를 서비스 지연과 대역폭 측면에서 정의하고, 정의된 서비스를 서비스 가치(Value of Service: VoS)라는 개념을 통해 표현한다. 이 모델과 VoS개념을 이용하여 각 세션에게 지연-대역폭 관점에서 공정한 서비스를 제공하는 스케줄링 알고리즘을 제안한다. 이 알고리즘을 통해, 각 세션에게 지연-대역폭 관점에서 공정서비스, 전송률을 보장하는 서비스를 제공하려고 한다.

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A Clock Generator with Jitter Suppressed Delay Locked Loop (낮은 지터를 갖는 지연고정루프를 이용한 클럭 발생기)

  • Nam, Jeong-Hoon;Choi, Young-Shig
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.7
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    • pp.17-22
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    • 2012
  • A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.