• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.675-678
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• 2015

In this paper, we proposed a multi-function conversion block for microwave receiver. The proposed multi-function conversion block is composed of a broadband voltage controlled oscillator and a dual-mode mixer. Depending on whether the bias voltage is supplied, the first IF(Intermediate Frequency) output frequency(4,595 MHz/6,045 MHz) needed in microwave receiver is converted to 720 MHz and the another IF output frequency(720 MHz) for receiving Ku-band has the multi-functional operations of the dual mode that are bypass and attenuation without frequency conversion. Implementation and measurement results show that each intermediate frequency has conversion loss characteristic according to the LO power. The LO power conversion loss of 4,595 MHz at the LO levels from 2 dBm to 4 dBm is 13 dB, another of 6,035 MHz is 12 dB and the other of 720 MHz is 7.0 dB.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1765-1768
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• 2005

Binary-search 알고리즘을 이용한 새로운 6-bit 300MS/s ADC 를 제안 하였다. 본 연구에서 제안된 ADC 는 저전력, 고속동작, 저해상도의 응용분야에 적합하도록 설계 되었다. 11 개의 rail-to-rail 비교기와 기준전압 발생기, 그리고 기준전압 제어회로로 구성 되었으며, 이는 기존의 구조와는 다른 전혀 새로운 형태로 제안된 것이다. 전력소모를 줄이기 위해 비교기 공유기술을 사용하였다. 또한 ADC 의 sub-block 인 rail-to-rail 비교기는 인버터 logic threshold 전압 값을 이용한 새로운 형태의 비교기를 제안하였다. 비교기는 인버터와 n-type preamp, p-type preamp 그리고 각각에 연결되는 latch 로 구성되었다. 기존의 rail-to-rail comparator 에 비해 입력 범위 전체 영역에서 일정한 gm 값을 얻을 수 있다. 실험결과 2.5V 공급전압에서, 17mW 의 전력 소모를 보이며, 최대 304MS/s 의 데이터 변환율을 가진다. INL 과 DNL 은 입력신호가 2.38Mhz 의 주파수를 가지는 삼각파일 때, 각각 ${\pm}0.54LSB$, ${\pm}1LSB$ 보다 작다. TSMC 0.25u 공정을 이용하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.613-623
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. The double frequency conversion and the active tracking filter in the front-end were used to reduce interference of the adjacent channels and multi-channels, which suppress If beat and image band. However, it was impossible to get frequency mapping between tracking filter and first VCO(Voltage Controlled Oscillator) in the double conversion digital TV tuner differing from conventional NTSC tuner. This paper, therefore, suggests the available structure and a new method for automatic frequency selection by obtaining the mapping of frequency characteristic over tracking voltage and the combined hardware which compose of Micro-controller, EEPROM, D/A(Digital-to-Analog Converter), OP amp and switch driver to solve above problems.

• Journal of IKEEE
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• v.18 no.3
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• pp.320-327
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• 2014

Recently, Importance of power management circuit technology is increased with the development of portable electric devices. This paper presents a high performance DC-DC buck converter for mobile applications. Especially, presented design have low ripple voltages and driving capability of large load current. A designed voltage mode 2-phase DC-DC converter is implemented in a $0.35{\mu}m$ CMOS process, and the overall size is $2.35{\times}2.35mm^2$. The peak efficiency is 91% with a 4MHz frequency and the maximum load current is 4A.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.50-54
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• 2016

본 논문에서는 전동차의 정차 시 발생하는 회생에너지를 Battery에 충전할 수 있는 전력 변환 장치를 제안한다. 제안된 전력 변환장치는 DC 1500~2000의 가선전압을 분압하여 저압스위칭 소자 적용하며, 고주파 절연 변압기를 적용하였다. 이를 통해 시스템의 스위칭 주파수를 상승시켜 수동 소자들의 사이즈 축소 및 비용 절감 효과를 높이고, 가선과 Battery의 전기적 절연으로 시스템의 안정성을 높였다. 또한 가선 전압 분압을 통해 입력 전압의 변화에 유동적으로 대응할 수 있으며, 시스템의 병렬 구성을 통해 용량의 확장성을 가지게 된다. 제안된 논문에서 제안된 회생에너지 전력 변환 장치는 20[kW] 회생 컨버터 모듈의 5직렬 구성을 통해 100[kW]급 회생 컨버터 유닛을 구성하였으며, 회생 컨버터 유닛을 5병렬로 구성하여 500[kW]급 회생 전력 변환시스템을 구성하였다. 제안된 회생에너지 시스템은 모의 가선 전압 장치 및 Battery 부하를 통해 시스템의 타당성을 검증 한다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.312-313
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• 2017

전력계통 주파수를 증대시키면 변압기를 비롯하여 전력변환기의 사이즈는 감소하나 부하에 따른 선로전압 강하가 크게 나타난다. 전력계통의 주파수는 전력전송이 이루어지는 거리에 따라 최적의 주파수로 운용한다면 전체시스템의 구성단가를 낮출 수 있다. 해외에서는 장거리전송을 위해 20[Hz] 전력전송에 대한 연구가 활발히 연구되고 있다. 항공모함과 같은 단거리 전력전송에서는 400[Hz] 전력전송을 사용하고 있다. 본 논문은 배전시스템의 주파수설정에 따른 변압기 및 전력변환기영역에서 장단점을 비교하여 경제성을 분석하여 마이크리드 시스템에 따라 그 적용 타당성을 연구하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.854-857
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• 2015

As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.3
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• pp.1700-1706
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• 2014

In this paper, a step down converter for LED backlight of mobile application has been proposed. The converter which is operated with 4 MHz high switching frequency is capable of reducing mounting area of passive devices consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. The control block consists of pulse width modulator, error amplifier and oscillator etc. Proposed step down converter has been designed and verified using a $0.35{\mu}m$ 1-poly 4-metal BCD process technology. Simulation results show that the output voltage is 1.8 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 KHz driven converter when the duty ratio is 0.4.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.