• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.11
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• pp.21-27
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• 2002

When decision-directed channel estimation is used for QAM-OFDM systems, the optimal shape of the two-dimensional filter depends on the amplitudes of the modulated symbols as well as the channel characteristics such as delay spread, Doppler frequency, and signal-to-noise ratio. While most conventional channel estimation methods did not consider the amplitudes of the modulated symbols because of the large computational complexity, we propose a simple channel estimation method for multi-level-amplitude-modulated systems. The proposed method can effectively reduce the noise variance of the estimates with small-sized filtering and there is a possibility of reducing the implementation cost and producing better results by avoiding the bias due to large filter sizes.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• The Journal of the Acoustical Society of Korea
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• v.20 no.5
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• pp.35-47
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• 2001

This paper describes an efficient harmonic-CELP speech coder by taking advantages of harmonic and CELP coders into account. According to frame voicing decision, the proposed harmonic-CELP coder adopts the RP-VSELP coder as a fast CELP in case of an unvoiced frame, or an improved harmonic coder in case of a voiced frame. The proposed coder has main features as follows: simple pitch detection, fast harmonic estimation, variable dimension harmonic vector quantization, perceptual weighting reflecting frequency resolution, fast harmonic synthesis, naturalness control using band voicing, and multi-mode. These features make the proposed coder require very low complexity, compared with HVXC coder To demonstrate the performance of the proposed coder, a 2.4 kbps coder has been implemented and compared with reference coders. From results of informal listening tests, the proposed coder showed good quality while requiring low delay and complexity.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.365-379
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• 2008

In this paper we consider technological requirements of the on-channel repeater to broadcast the terrestrial digital multimedia broadcasting (T-DMB) signals using single frequency networks (SFN) and propose the configuration and implementation method of the equalization on-channel repeater (OCR) that meet such requirements. The proposed equalization OCR not only has short time delay, but shows high output power and good quality of output signal by removing a feedback signal due to incomplete antenna isolation and multipath signal existing between the main transmitter and the OCR. In addition, computer simulations and laboratory tests results are provided to figure out performance of the proposed equalization OCR.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.6
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• pp.403-410
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• 2008

This paper suggests a standstill estimator to accurately identify induction motor (IM) parameters necessary for the vector control. A mathematical model that faithfully represents the general skin effect is introduced. Then, two exciting signals with a different frequency are sequentially injected to track the parameters based on the skin effect of the rotor bar. Little knowledge of the unknown motor allows the proposed methodology to employ a closed-loop control of an injected current, rather than open-loop voltage injection approaches. Subsequently, this control scheme proactively prevents electrical accidents resulting from an inadequate open-loop voltage injection. We develop a specialized offline commissioning test to compensate the phase delay resulting from the drive, which significantly affects the precision of the IM parameters. The effectiveness of the identification technique is validated by means of experiments performed on the three different IMs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.1057-1064
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• 2007

Cognitive radio(CR) technique which utilizes empty frequency bands allocated to private business but not being used temporally has been researched. According to the standard, CR users detect the primary user using the same channel, CR users should move to the another channel to guarantee the primary user's decodability. Thus, CR systems cannot use the same channel and support the CR user's QoS(Quality of Service) during the channel moving time. In this paper, we propose a radio resource sharing method that CR basestation controls the transmission power with the primary user's SNR(Signal to Noise Ratio) to increase the spectral efficiency of area and to minimize the outage of CR users. In addition, computer simulation demonstrates show that the proposed method improved spectral efficiency of area and decreased outage probability of CR users.

• Journal of Biomedical Engineering Research
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• v.23 no.2
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• pp.87-99
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• 2002

This paper describes a method for overcoming the motion artifacts inherent in synthetic aperture(SA) imaging. based on the investigation results as to the influence of a target motion on synthetic aperture techniques. This method uses a region-based motion compensation approach in which only the axial motion is estimated and compensated for a given region of interest(ROI) under the assumption that the whole ROI moves uniformly The estimated axial motion is calculated with a crosscorrelation(CC) method at the Point where the focused signal has the maximum energy within the ROI. We also presents a method for estimating the axial motion using the autocorrelation(AC) method that is widely used to estimate average Doppler frequency Both computer simulations and in vivo experiments show that the proposed methods can improve greatly the spatial resolution and SNR of ultrasound imaging by implementing the SA techniques for two-way dynamic focusing without motion artifacts. In addition the AC-barred motion compensation method provides almost the same results as the CC-based one, but with a dramatically reduced computational complexity.