• Journal of Korean Society of Coastal and Ocean Engineers
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• v.29 no.6
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• pp.286-304
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• 2017

In this study, we proposed a new-type of circular perforated caisson breakwater consisting of a bundle of latticed blocks that can be applied to a small port such as a fishing port, and numerically investigated the hydraulic characteristics of the breakwater. The numerical method used in this study is OLAFOAM which newly added wave generation module, porous media analysis module and reflected wave control module based on OpenFOAM that is open source CFD software published under the GPL license. To investigate the applicability of OLAFOAM, the variations of wave pressure acting on the three-dimensional slit caisson were compared to the previous experimental results under the regular wave conditions, and then the performance for irregular waves was examined from the reproducibility of the target irregular waves and frequency spectrum analysis. As a result, a series of numerical simulations for the new-type of circular perforated caisson breakwaters, which is similar to slit caisson breakwater, was carried out under the irregular wave actions. The hydraulic characteristics of the breakwater such as wave overtopping, reflection, and wave pressure distribution were carefully investigated respect to the significant wave height and period, the wave chamber width, and the interconnectivity between them. The numerical results revealed that the wave pressure acting on the new-type of circular perforated caisson breakwaters was considerably smaller than the result of the impermeable vertical wall computed by the Goda equation. Also, the reflection of the new-type caisson breakwater was similar to the variation range of the reflection coefficient of the existing slit caisson breakwater.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2000.04a
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• pp.5-5
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• 2000

액체 추진 로켓 엔진의 고주파 연소 불안정 관련 이론은 대체로 연소기 내부의 음향 공명 모드와 분무 연소 과정의 상호 작용을 구동 메커니즘으로 전제하며 Rayleigh Criterion의 재해석에 기초하여 불안정성 평가를 위한 매개변수를 도입하고 연소 불안정성을 예측한다. 여기에는 음향장 분석 이론, 음향 불안정 이론, 연소응답 및 기화반응 이론 등이 포함된다. 본 연구에서는 LOX/RPl 추진제 조합의 액체 추진 로켓 엔진 연소기를 대상으로 다차원 순수 음향장 해석과 연소-음향장 분석을 통해 대상 엔진의 고주파 연소 불안정 특성을 예측하였다. 수동 제어 기기인 음향공 설치에 따른 연소기의 음향장 및 연소-음향장의 특성 변화를 고찰하고 위 결과를 종합하여 음향공의 연소 불안정 억제 성능 및 대상 엔진의 연소 불안정성을 평가하였다. 연소기 형상 및 음향공 설치에 따른 다차원 순수 음향장 해석은 상용코드인 ANSYS를 사용하여 수행하였다. 내부 유체는 압축성, 비점성 유체로 유체의 평균 유동은 무시하며 위치에 관계없이 균일한 물성치를 부여하였다. 정상상태 연소과정을 가정하고 평형 화학을 이용한 분석 결과로부터 연소 기체의 관련 물성치를 결정하였다. 연소기 길이 방향, 반경 방향, 원주 방향 격자점들의 음향 특성을 주파수 영역에 대해 해석하고 3차원 음향 모드 형상을 토대로 음향장을 분석하였다. 연소-음향장 해석은 음향 불안정 이론 중 n- $\tau$ 2 매개변수 기법을 사용하였다. 연료 액적의 분무 연소 과정을 1차원적으로 가정하고 정상상태의 평형 화학 계산 결과를 이용하여 엔진의 연소면을 1차원적으로 설정하였다. 상류 연소응답과 중립 안정 곡선을 토대로 대상 엔진의 연소 불안정 특성을 분석하였다.구 분석 결과 기술적 문제점으로는 배기 가스온도가 낮은데 따른 출구 부분의 Bearing, Sealing이 문제가 될 수 있다고 판단되며 배기 가스 자체에 대기 공기중에 함유되어 있던 습기가 얼어붙는(Icing화) 문제가 발생하기 때문에 배기가스의 Icing을 방지하기 위하여 압축기 끝단에서 공기를 추출하여 배기부분에 송출할 필요성이 있는 것으로 판단되었다. 출구가스의 기체 유동속도가 매우 빠르므로 (100-l10m.sec) 이를 완화하기 위한 디퓨저의 설계가 요구된다고 판단된다. 또 연소기 후방에 물을 주입하는 경우 열교환기 및 기타 부분품에 발생할 수 있는 부식 및 열교환 효율 저하도 간과할 수 없는 문제로 파악되었다. 이러한 기술적 문제가 적절히 해결되는 경우 비활성 가스 제너레이터는 민수용으로는 대형 빌딩, 산림, 유조선 등의 화재에 매우 적절히 사용되어 질 수 있을 뿐 아니라 군사적으로도 군사작전 중 및 공군 기지의 화재 그리고 지하벙커에 설치되어 있는 고급 첨단 군사 장비 등의 화재 뿐 아니라 대간첩작전 등에 효과적으로 활용될 수 있을 것으로 판단된다.가 작으며, 본 연소관에 충전된 RDX/AP계 추진제의 경우 추진제의 습기투과에 의한 추진제 물성 변화는 미미한 것으로 나타났다.의 향상으로, 음성개선에 효과적이라고 사료되었으며, 이 방법이 편측 성대마비 환자의 효과적인 음성개선의 치료방법의 하나로 응용될 수 있으리라 생각된다..7%), 혈액투석, 식도부분절제술 및 위루술·위회장문합술을 시행한 경우가 각 1례(2.9%)씩이었다. 13) 심각한 합병증은 9례(26.5%)에서 보였는데 그중 식도협착증이 6례(17.6%), 급성신부전증 1례(2.9%), 종격동기흉과 폐염이 병발한 경우와 폐염이 각 1례(2.9%)였다. 14)

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.671-680
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• 2005

The CFL linearisation chip which is one of key devices in ultra-narrowband mobile radio transmitter using CQPSK digital modulation method is designed and implemented with $0.35{\mu}m$ CMOS technology. The reduced size and low cost of transmitter are available by the use of direct-conversion and CFL ASIC chip, which improve the power effi챠ency and linearity of transmitting path. In addition, low power operation is possible through CMOS technology The performance test results of transmitter show -25 dBc improvement of IMD level at the 3 kHz frequency offset and then satisfy FCC 47 CFR 90.210 E emission mask in the operation of CFL ASIC chip. At that time, the transmitting power is about PEP(Peak-to-Envelope Power) 5 W. The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.138-148
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• 2001

Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.3 s.32
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• pp.17-22
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• 2004

The microwave dielectric properties of $CaZrO_3$ ceramics with addition of $CaTiO_3$ were studied. The effect of glass addition on the low-temperature sintering and microwave dielectric properties of $CaZrO_3-CaTiO_3$ ceramics were also evaluated to develop the materials for functional substrates of low-temperature co-fired ceramics. When $10-20 wt\%$ of lithium borosilicate glass was added, the sintering temperature of the $CaZrO_3-CaTiO_3$ ceramics decreased from $1450^{\circ}C$ to below $900^{\circ}C$. As the $T_f$ of glass frits and $CaZrO_3$ are slightly negative and that of $CaTiO_3$ is significantly positive, zero $T_f$ could be realized by mixing an appropriate amount of $CaTiO_3$ with $CaZrO_3$. The $CaZrO_3-CaTiO_3$ ceramics sintered at $875^{\circ}C$ with $15wt\%$ glass frits showed the relative density of $98\%$, permittivity of 23, quality factor of 2500 GHz, and temperature coefficient of resonant frequency of $ -3 ppm/^{\circ}C$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.573-582
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• 2010

In this paper, X-band transceiver for high resolution wideband SAR systems is designed and fabricated. Also as a technique for enhancing the performance, error compensation algorithm is presented. The transceiver for SAR system is composed of transmitter, receiver, switch matrix and frequency generator. The receiver especially has 2 channel mono-pulse structure for ground moving target indication. The transceiver is able to provide the deramping signal for high resolution mode and select the receive bandwidth for receiving according to the operation mode. The transceiver had over 300 MHz bandwidth in X-band and 13.3 dBm output power which is appropriate to drive the T/R module. The receiver gain and noise figure was 39 dB and 3.96 dB respectively. The receive dynamic range was 30 dB and amplitude imbalance and phase imbalance of I/Q channel was ${\pm}$0.38 dBm and ${\pm}$3.47 degree respectively. The transceiver meets the required electrical performances through the individual tests. This paper shows the pulse error term depending on SAR performance was analyzed and range IRF was enhanced by applying the compensation technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1050-1060
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• 2009

In this paper, a X-Band T/R-module for SAR(Synthetic Aperture Radar) systems based on active phased array antennas is designed and fabricated. The T/R modules have a and width of more than 800 MHz centered at X-Band and support dual, switched polarizations. The output power of the module is 7 watts over a wide bandwidth. The noise figure is as low as 3.9 dB. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit digital attenuator, respectively. Further the fabricated T/R module has est and calibration port with directional coupler and power divider. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. RMS gain error is less than 0.8 dB max. in Rx mode, and RMS phase error is less than $4^{\circ}$ max. in Rx/Tx phase under all operating frequency band, or the T/R module meet the required electrical performance m test. This structure an be applied to active phase array SAR Antennas.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1061-1070
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• 2009

In this paper, we have designed TDL(True-time Delay Line) for eliminating beam-squint occurring in active phased array antenna with large electrical size operated in wide bandwidth, and have tested its electrical performance. The proposed TDL device is composed of 4-bit microstrip delay line structure and MMIC amplifier for compensation of the delay-line loss. The measured results of gain and phase versus delay state satisfy the electrical requirements, also P1dB output power and noise figure meet the requirement. To verify the performance of fabricated TDL, we have simulated the beam patterns of wide-band active phased array antenna using the measured results and have certified the beam pattern compensation performance. As a result of simulated beam pattern compensation with respect to the 675.8 mm size antenna which is operated in X-band, 800 MHz bandwidth, we have reduced the beam squint error of ${\pm}1^{\circ}$ with ${\pm}0.1^{\circ}$. So this TDL module is able to be applied to active phase array antenna system.

• Journal of the Korean Vacuum Society
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• v.22 no.3
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• pp.168-173
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• 2013

In this paper, we would like to introduce Electron Relay Enhancer (ERE), a supplementary device, which improves commercial solar cell efficiency minimizing electron-hole recombination of solar cell. The ERE in this study is mainly composed of two capacitors which are connected to AC power source and bridge diode system which controls electron flow direction. Two capacitors repeat collecting electrons from solar cell and pumping the collected electrons to load resistance or inverter through the bridge diode system. While one positively charged capacitor collect electrons, the other negatively charged one pumps electrons. A positively charged capacitor pulls the more exited electrons from the solar cell, before the exited electrons recombine the holes in solar cell. That is why the ERE system enhances solar cell efficiency. As a result, the measured power increase of the solar cell with the ERE is varied from 5.9 W to 25.6 W in each experimental condition. Maximal increase rate of the solar cell power with ERE is 30.8% of solar cell power without ERE.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.