• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.11
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• pp.523-530
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• 2018

It has been studied over the long time for the high efficiency and high power density of the power converter. It is possible to obtain higher power conversion efficiency and small volume by increasing switching frequency, however, the switching loss is also increased. The soft switching technique can overcome of the above deficiency. The design and analysis method for ZVS(Zero Voltage Switching) Phase Shifte Full bridge converter is presented in this paper. The power transfer depends on the phase difference between two legs of the power stage and the maximum power conversion efficiency is achieved by the optimum leakage inductance value. The waveform of the current and voltage of the operational mode is analysed and the corresponding switch status is plotted as on/off status. A ZVS full bridge converter for a communication rectifier with 2kW output power is implemented and its performance are verified through PSIM software simulation and experimental results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.78-84
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• 2008

In this paper, the reconfigurable annular ring slot antenna with circular polarization diversity is proposed for SDMB(Satellite Digital Multimedia Broadcasting) system. The proposed antenna consists of a ring slot with four tuning stubs. Four PIN diodes are attached to switch circular polarization diversity. By switching the diodes ON or OFF, the proposed antenna can be operated either RHCP mode or LHCP mode. The experimental result shows that the proposed antenna has an impedance bandwidth(VSWR${\leq}$2) of 570MHz(2.47-3.04GHz) at LHCP mode, an impedance bandwidth (VSWR${\leq}$2) of 560MHz(2.45-3.01GHz) at RHCP mode, a maximum gai of 3.1dBi at RHCP mode, 4.76dBi at LHCP mode. The 3dB CP bandwidth of about 100MHz at both RHCP and LHCP mode is achieved at the center frequency 2.63GHz. The proposed antenna is suitable for application such as mobile satellite communications, WLAN(Wireless Local Area Networks), and broadband wireless communication systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.85-91
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• 2010

In this paper, a new microstrip antenna using asymmetric U-shaped slotted ground is proposed for a switchable circular polarization sense. The proposed antenna is achieved a circularly polarization from orthogonal E-field distributions with 90 degree phase difference due to the asymmetrical U-shaped slot. Moreover, the circular polarization sense of the proposed antenna can be easily switchable with changing the symmetric plane of the U-shaped slots. As a result, the proposed antenna is implemented by two PIN diodes with two different bias condition for ON/OFF states. The measured axial ratios are about 1.5 dB without the dependence of the polarization sense and 3-dB axial ratio bandwidth are achieved 29 MHz with respect to about 1.2 % at 2.46 GHz operating frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.9-12
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• 2006

We have designed and fabricated micro power generators by electroplating which is important in MEMS(micro electro mechanical system) technique. We have electroplated MEMS coils on the glass substrates and have chosen one of these coils for experiments. The thickness, width, and length of the coil are $7{\mu}m,\;20{\mu}m$, and 1.6 m, respectively. We have analyzed the structure of MEMS coil by SEM. We have made a vibrating system for reproducible results in measurement. With reciprocating a magnet on the surface of a fabricated winding coil, the micro power generator produce an alternating voltage. We have changed the vibrational frequency from 0.5 Hz to 8 Hz. The generated voltage was 106 mV at 3 Hz and 198 mV at 6 Hz. We aim at the micro power generator which can change vibration energy to useful electric energy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.