• Journal of KIISE:Computing Practices and Letters
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• v.7 no.5
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• pp.402-415
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• 2001

Advantages of flash memories are their shock resistance and fast read speed, which is much faster than that of a HDD. Because of these characteristics, they are increasingly used in the traditional household electric appliance and portable handset and therefore, development of file systems which use them as storage medium is increasingly needed. But they have two problems as storage medium. First, data stored in them cannot be overwritten: it must be erased before new data can be stored. Unfortunately, this erase operation usually takes about one second. Consequently, updating data in flash memories takes long time. In this paper, their problem is solved by using a data update mechanism like LFS(Log-structured File System). Second, their erase operations are restricted. We propose novel cleaning policy in order to increase the life cycle. We implemented FAT file system, which is suitable to small storage medium and solved problems, which usually happen in implementing FAT. We evaluated the performance of sequential writes and random writes on our implemented flash file system.

• Journal of Broadcast Engineering
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• v.27 no.1
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• pp.104-123
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• 2022

Style transfer based on neural network provides very high quality results by reflecting the high level structural characteristics of images, and thereby has recently attracted great attention. This paper deals with the problem of resolution limitation due to GPU memory in performing such neural style transfer. We can expect that the gradient operation for style transfer based on partial image, with the aid of the fixed size of receptive field, can produce the same result as the gradient operation using the entire image. Based on this idea, each component of the style transfer loss function is analyzed in this paper to obtain the necessary conditions for partitioning and padding, and to identify, among the information required for gradient calculation, the one that depends on the entire input. By structuring such information for using it as auxiliary constant input for partition-based gradient calculation, this paper develops a recursive algorithm for super high-resolution image style transfer. Since the proposed method performs style transfer by partitioning input image into the size that a GPU can handle, it can perform style transfer without the limit of the input image resolution accompanied by the GPU memory size. With the aid of such super high-resolution support, the proposed method can provide a unique style characteristics of detailed area which can only be appreciated in super high-resolution style transfer.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.31-40
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• 2012

u-GIS DSMSs have been researched to deal with various sensor data from GeoSensors in ubiquitous environment. Also, they has been more important for high availability. The data from GeoSensors have some characteristics that increase explosively. This characteristic could lead memory overflow and data loss. To solve the problem, various load shedding methods have been researched. Traditional methods drop the overloaded tuples according to a particular criteria in a single server. Tuple deletion sensitive queries such as aggregation is hard to satisfy accuracy. In this paper a dual processing load shedding method is suggested to improve the accuracy of aggregation in clustering environment. In this method two nodes use replicated stream data for high availability. They process a stream in two nodes by using a characteristic they share stream data. Stream data are synchronized between them with a window as a unit. Then, processed results are merged. We gain improved query accuracy without data loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.183-189
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• 2018

This paper proposes distributed file placement and coverage expansion techniques for mitigating the traffic bottleneck in backhaul for small-cell networks. In order to minimize the backhaul load with limited memory space, the proposed scheme controls the coverage and file placement of base station according to file popularity distribution and memory space of base stations. In other words, since the cache hit ratio is low when there is small memory capacity or widespread file popularity distribution, the base stations expand its coverage and cache different set of files for the user located in overlapped area to exploit multiple cached file sets of base stations. Our simulation results show that the proposed scheme outperforms the conventional cache strategy in terms of network throughput when there is small memory capacity or widespread file popularity distribution.

• Journal of the Korea Society of Computer and Information
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• v.15 no.6
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• pp.57-64
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• 2010

Due to the limited storage space in video proxy server, it is often required to replace the old video data which is not serviced for long time with the newly requested video. This replacement causes the service delay and increase of network traffic. To circumvent this problem, we propose the an efficient replacement scheme in a video proxy server. In addition, we present a video data management technique for decreasing the number of replacement in video proxy server. For this purpose, we employ a memory in video proxy server. If the video segment which is loaded in memory is requested once again by a different user, this segment is resided in memory. The video in the memory is stored in the video proxy server depending on the consuming pattern by users. The simulation results show that the proposed algorithm performs better than other algorithms in terms of packet hit rate and number of packet replacement.