• Title/Summary/Keyword: 제안치

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Automatic Threshold-decision Algorithm using the Average and Standard Deviation (평균과 표준편차를 이용한 자동 임계치-결정 알고리즘)

  • Ko, Kyong-Cheol;Rhee, Yang-Won
    • The Journal of Korean Association of Computer Education
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    • v.8 no.6
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    • pp.103-111
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    • 2005
  • This paper presents a novel automated threshold-decision algorithm that uses the mean and standard-deviation values obtained from the difference values of consecutive frames. At first, the calculation of difference values is obtained by the weighted ${\chi}^2$-test algorithm which was modified by joining color histogram to ${\chi}^2$-test algorithm. The weighted ${\chi}^2$-test algorithm can subdivide the difference values by imposing weights according to NTSC standard. In the first step, the proposed automatic threshold-decision algorithm calculates the mean and standard-deviation value from the total difference values, and then subtracts the mean value from the each difference values. In the next step, the same process is performed on the remained difference values, and lastly, the threshold is detected from the mean when the standard deviation has a maximum value. The proposed method is tested on various video sources and, in the experimental results, it is shown that the proposed method efficiently estimates the thresholds and reliably detects scene changes.

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Assessment of Design Criteria for Bearing Capacity of Rock Socketed Drilled Shaft (암반에 근입된 현장타설말뚝의 지지력 산정기준에 대한 평가)

  • 백규호;사공명
    • Journal of the Korean Geotechnical Society
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    • v.19 no.4
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    • pp.95-105
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    • 2003
  • The existing design criteria f3r the estimation of ultimate bearing capacity of drilled shaft socketed into rock masses are mainly obtained from the ultimate pile load capacities, which are determined by inconsistent failure criteria. Therefore, these design criteria generally produce difffrent predictions even for drilled shaft in the same condition. In this paper, the accuracies of the existing design criteria are investigated to develop an optimized design process for drilled shaft socketed into rock masses. Reasonable and consistent ultimate capacities of drilled shafts socked into rock masses, necessary far the check of accuracies of predictions, are determined by applying a specific failure criterion to a total of 11 pile load test results. A comparison between the predicted and the measured load capacities shows that ultimate base load capacities calculated from Zhang and Einstein's equation and NAVFAC are close to the measured values. Rosenberg and Journeaux's equation produces satisfactory prediction f3r ultimate side load capacity.

A Performance Improvement on Navigation Applying Measurement Estimation in Urban Weak Signal Environment (도심에서의 측정치 추정을 적용한 항법성능 향상 연구)

  • Park, Sul Gee;Cho, Deuk Jae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.11
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    • pp.2745-2752
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    • 2014
  • In recent years, Transport Demand Management has been conducted for the efficient management of transport. In ITS applications in particular, the prerequisite is accurate and reliable positioning. However, the major problems are satellite signal outage, and multipath. This paper proposes that outage and multipath measurement can be detected and estimated using elevation angle and signal to noise ratio data association relation in stand-alone GPS. In order to verify the performance of the proposed method, it is then evaluated by the car test. the evaluation test environment has low accuracy and unreliable positioning because of signal outage or multipath such as steep hill and high buildings. In the evaluation test result, 918times abnormal signal occurred and it was confirmed that the proposed method showed more improved 9.48m(RMS) horizontal positioning error than without proposed method.

On the Estimation of Ship's Approach Speed Limit to the Pier to Prevent Breaking of Mooring Rope (계류삭 파단 방지를 위한 선박의 한계치 접안 속력 추정에 관한 연구)

  • Kim, Dae-Jeong;Lee, Chun-Ki;Yim, Jeong-Bin
    • Journal of Navigation and Port Research
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    • v.42 no.6
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    • pp.388-394
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    • 2018
  • When a ship is berthing on the pier using a mooring rope, excessive ship speeds may cause accidents where mooring rope is cut off. In order to prevent the mooring rope from breaking, there is need to know the approach speed limit of the ship. The purpose of this study is to estimate the berthing speed limit of a ship to prevent mooring fracture. Focus will be made to when the speed of the ship is unknown. In this study, we propose a method and procedure for estimating the berthing-speed limit based on the theory of ship resistance and the elasticity of the mooring rope. This method was found to be effective as it was observed that the mooring rope cannot be broken when it is estimated that the berthing-speed of a 135K LNG vessel, IWRC, and $6{\times}36$ steel wire mooring rope. The method proposed in this study will significantly contribute to preventing actual accidents related to mooring lines.

Estimation of Shear-Wave Velocities of Layered Half-Space Using Full Waveform Inversion with Genetic Algorithm (유전 알고리즘을 활용한 완전파형역산 기법의 층상 반무한 지반 전단파 속도 추정)

  • Lee, Jin Ho;Lee, Se Hyeok
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.34 no.4
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    • pp.221-230
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    • 2021
  • This paper proposes full waveform inversion (FWI) for estimating the physical properties of a layered half-space. An FWI solution is obtained using a genetic algorithm (GA), which is a well-known global optimization approach. The dynamic responses of a layered half-space subjected to a harmonic vertical disk load are measured and compared with those calculated using the estimated physical properties. The responses are calculated using the thin-layer method, which is accurate and efficient for layered media. Subsequently, a numerical model is constructed for a layered half-space using mid-point integrated finite elements and perfectly matched discrete layers. An objective function of the global optimization problem is defined as the L2-norm of the difference between the observed and estimated responses. A GA is used to minimize the objective function and obtain a solution for the FWI. The accuracy of the proposed approach is applied to various problems involving layered half-spaces. The results verify that the proposed FWI based on a GA is suitable for estimating the material properties of a layered half-space, even when the measured responses include measurement noise.

An Experiment for Determining Threshold of Defect Prediction Models using Object Oriented Metrics (객체지향 메트릭을 이용한 결함 예측 모형의 임계치 설정에 관한 실험)

  • Kim, Yun-Kyu;Chae, Heung-Seok
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.12
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    • pp.943-947
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    • 2009
  • To support an efficient management of software verification and validation activities, many defect prediction models have been proposed based on object oriented metrics. In order to apply defect prediction models, we need to determine a threshold value. Because we cannot know actually where defects are, it is difficult to determine threshold. Therefore, we performed a series of experiments to explore the issue of determining a threshold. In the experiments, we applied defect prediction models to other systems different from the system used in building the prediction model. Specifically, we have applied three models - Olague model, Zhou model, and Gyimothy model - to four different systems. As a result, we found that the prediction capabilities varied considerably with a chosen threshold value. Therefore, we need to perform a study on the determination of an appropriate threshold value to improve the applicably of defect prediction models.

Design of Synchronous Quaternary Counter using Quaternary Logic Gate Based on Neuron-MOS (뉴런 모스 기반의 4치 논리게이트를 이용한 동기식 4치 카운터 설계)

  • Choi Young-Hee;Yoon Byoung-Hee;Kim Heung-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.3 s.333
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    • pp.43-50
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    • 2005
  • In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

A Frame Unit Based Adaptive Pruning Algorithm for the East Speech Recognition (음성인식의 고속화를 위한 프레임 단위 적응 프루닝 알고리즘)

  • Hwang Cheol-Jun;Oh Se-Jin;Kim Bum-Koog;Jung Ho-Youl;Chung Hyun-Yeol
    • Proceedings of the Acoustical Society of Korea Conference
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    • autumn
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    • pp.183-186
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    • 2000
  • 본 논문에서는 인식이 진행되는 동안 탐색 공간을 효과적으로 줄임으로써 음성인식의 고속화를 달성할 수 있는 새로운 프레임 단위 적응 프루닝 알고리즘을 제안하고 실험을 통하여 그 유효성을 확인하였다. 이것은 앞 프레임과 뒤 프레임 사이의 최대확률은 높은 상관성을 가지므로 프루닝 문턱치를 앞 프레임의 최대 확률로부터 효과적으로 구할 수 있다는 사실에 근거를 두고있다. 이 방법에서는 앞 프레임의 최대 우도 확률과 후보 확률들의 조합으로 현재 프레임의 프루닝 문턱치를 갱신함으로써 현재 프레임의 문턱치를 인식 과정 중에 얻을 수 있기 때문에, 인식 태스크가 바뀌어도 문턱치를 구하기 위한 사전 실험을 수행할 필요가 없게 된다. 또한, 프레임 단위로 적응적으로 얻어진 문턱치는 다른 환경 하에서도 인식 속도의 향상을 가져올 수 있게 된다. 제안된 알고리즘의 유효성을 확인하여 위하여 한국어 주소 인식 시스템에 적용하였다. 본 시스템은 48개의 유사음소단위(PLUs)를 인식의 기본단위로 하고, 적응알고리즘으로는 최대사후확률추정법((MAP: Maximum A Posteriori Probability Estimation)을, 인식 알고리즘으로는 OPDP(One Pass Dynamic Programming)법을 이용하였다 남성화자 3인이 25개의 연결 주소명을 대상으로 인식 실험을 수행한 결과, 제안된 프레임단위 적응프루닝 문턱치를 적용한 경우를 기존의 고정 프루닝 문턱치와 가변 프루닝 문턱치를 적용한 경우와 비교하였을 때 인식률의 변화 없이 탐색공간이 상대적으로 각각 $14.4\%$9.14\%가 감소되어 제안된 프레임 단위 적응 프루닝 알고리즘의 유효성을 확인할 수 있었다. 시,공간적 분포 특성이 구체적으로 규명되면 보다 정확한 음장변화 추정이 이뤄져야 할 것으로 보인다. 또한 내부파와 음파의 상대적인 진행 방향에 따라 음장변화가 크게 다를 것이 예상되므로 이를 규명하기 위해서는 궁극적으로 3차원적인 음장분포 연구가 필요하다. 음향센서를 해저면에 매설할 경우 수충의 수온변화와 센서 주변의 수온변화 사이에는 어느 정도의 시간지연이 존재하게 되므로 이에 대한 영향을 규명하는 것도 센서의 성능예측을 위해서 필요하리라 사료된다.가지는 심부 가스의 개발 성공률을 증가시키기 위하여 심부 가스가 존재하는 지역의 지질학적 부존 환경 및 조성상의 특성과 생산시 소요되는 생산비용을 심도에 따라 분석하고 생산에 수반되는 기술적 문제점들을 정리하였으며 마지막으로 향후 요구되는 연구 분야들을 제시하였다. 또한 참고로 현재 심부 가스의 경우 미국이 연구 개발 측면에서 가장 활발한 활동을 전개하고 있으며 그 결과 다수의 신뢰성 있는 자료들을 확보하고 있으므로 본 논문은 USGS와 Gas Research Institute(GRI)에서 제시한 자료에 근거하였다.ऀĀ耀Ā삱?⨀؀Ā Ā?⨀ጀĀ耀Ā?돀ꢘ?⨀硩?⨀ႎ?⨀?⨀넆돐쁖잖⨀쁖잖⨀/ࠐ?⨀焆덐瀆倆Āⶇ퍟ⶇ퍟ĀĀĀĀ磀鲕좗?⨀肤?⨀⁅Ⴅ?⨀쀃잖⨀䣙熸ጁ↏?⨀

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Improvement of Subspace Iteration Method with Shift (쉬프트를 갖는 부분공간 반복법의 개선)

  • Jung, Hyung Jo;Kim, Man Cheol;Park, Sun Kyu;Lee, In Won
    • Journal of Korean Society of Steel Construction
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    • v.10 no.3 s.36
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    • pp.473-486
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    • 1998
  • A numerically stable technique to remove the limitation in choosing a shift in the subspace iteration method with shift is presented. A major difficulty of the subspace iteration method with shift is that because of singularity problem, a shift close to an eigenvalue can not be used, resulting in slower convergence. This study solves the above singularity problem using side conditions without sacrifice of convergence. The method is always nonsingular even if a shift is an eigenvalue itself. This is one of the significant characteristics of the proposed method. The nonsingularity is proved analytically. The convergence of the proposed method is at least equal to that of the subspace iteration method with shift, and the operation counts of above two methods are almost the same when a large number of eigenpairs are required. To show the effectiveness of the proposed method, two numerical examples are considered.

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A Study of FPGA Algorithm for consider the Power Consumption (소모전력을 위한 FPGA 알고리즘에 관한 연구)

  • Youn, Choong-Mo;Kim, Jae-Jin
    • Journal of Digital Contents Society
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    • v.13 no.1
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    • pp.37-41
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    • 2012
  • In this paper, we proposed FPGA algorithm for consider the power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within FPGA. Separated the feasible cluster reduced power consumption using glitch removal method. Glitch removal appled delay buffer insertion method by signal process within the feasible cluster. Also, removal glitch between the feasible clusters by signal process for circuit. The experiments results show reduction in the power consumption by 7.14% comparing with that of [9].