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A study on the design of general division operator for the divisor with a small number in RNS (소(少) 제수용 잉여수계 제산 연산기 설계에 관한 연구)

  • Kim, Yong-Sung
    • The Journal of Information Technology
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    • v.7 no.2
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    • pp.19-28
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    • 2004
  • Many kind of operators using Residue Number System are used to design the special purpose processor for many merits in Digital Signal Processing, Computer Graphics, etc. But It get demerits for general division and the magnitude comparison. In this paper, general division operator for divisor with a small number in RNS is proposed. If the result of division using the multiplicative inverse has remainder, the quotient of this is larger than maximum quotient of division that has the same divisor to dividend of the maximum size. This condition is used for the ending condition of the recursive operation. And, the divisor is substitute for the compared value of quotients. So, the proposed division operator has a small size and fine operation speed, but with the limitation of divisor.

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A Design and Implementation of the Division/square-Root for a Redundant Floating Point Binary Number using High-Speed Quotient Selector (고속 지수 선택기를 이용한 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 구현)

  • 김종섭;조상복
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.5
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    • pp.7-16
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    • 2000
  • This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

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Design of a high-performance floating-point unit adopting a new divide/square root implementation (새로운 제산/제곱근기를 내장한 고성능 부동 소수점 유닛의 설계)

  • Lee, Tae-Young;Lee, Sung-Youn;Hong, In-Pyo;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.79-90
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    • 2000
  • In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

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New VQB divide/square root operator that uses Booth algorithm (Booth 알고리즘을 이용한 새로운 VQB 제산/제곱근 연산기의 설계)

  • 이성연;이태영;이용석
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.380-383
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    • 1999
  • 본 논문은 Booth 알고리즘을 사용하는 새로운 VQB제산기를 제안한다. 본 논문은 Macsorley의 제산 알고리즘에 기본 원리가 같은 제곱근 알고리즘을 추가하였으며, 이를 VQB 알고리즘이라고 명명하였다. 본 논문은 VQB 제산기의 두 가지 설계를 구현하였다. 하나는 계수를 사용하지 않는 설계 (A) 이며, 둘은 [1/2, 2]의 계수군을 사용하는 설계 (B)이다. 설계 (A)는 순환할때마다 2.54 비트의 부분 몫을 결정하며 설계 (B)는 2.74 비트를 결정한다. 본 논문은 VQB 제산기의 성능지표를 좌우하는 제곱근을 위주로 하여 SRT 제산기와의 비교를 시도하였다. VQB 는 처리량과 설계 노력 면에서 SRT를 앞서며, 면적과 임계지연 면에서는 SRT와 서로 견줄만한 수준이다. 표준셀 0.35㎛ CMOS 공정으로 구현될 때, 설계 (A)의 임계지연은 9.69㎱ 이며, 설계 (B)는 11.05㎱이다.

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Effects of Glycerin and Sorbitol on the Ageing of Aluminum Hydroxide Gel (제산제에 관한 연구 (제 8 보) Glycerin 또는 Sorbitol의 첨가가 수산화 알루미늄.겔의 노화에 미치는 영향)

  • 유병설;홍문화
    • YAKHAK HOEJI
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    • v.6 no.2
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    • pp.13-17
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    • 1962
  • The effects of glycerin and sorbitol and ageing of antacid activity of aluminum hydroxide gel has been described. The results under accelerated temperatures showed sorbitol had excellent stabilizing effect and glycerin had promoting effect by contraries.

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Dwell time calculation algorithm in aspherical lens polishing with discrete annular tool path (이산 환형 방식의 비구면 렌즈 연마 경로에서 체재 시간 제산 알고리듬)

  • Lee Ho Cheol;Yang Min Yang
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.14 no.2
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    • pp.14-20
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    • 2005
  • This paper describes a dwell time calculation algorithm for polishing tool path generation in the small toot polishing process of the axis-symmetrical lens. Generally dwell time control in the polishing machines means that small polishing tool stays for a dwell time at the specific surface position to get the expected polishing depth. Polishing depth distribution on an aspherical lens surface consists of the superposition of the local polishing depth at the each dwell position. Therefore, tool path generation needs each dwell time together with tool positioning data during the polishing tool movements on the aspherical lens surface. The linear algebraic equation of removal depth removal matrix and dwell time is formulated. Parametric effects such as the dwell d interval are simulated to validate the dwell time calculation algorithm.

Study on the Stability of Ascorbic acid in several Antacid Preparations (분말성제제(粉末性製劑)의 안정성(安定性)에 관(關)한 연구(硏究) -수종제산제중(數種制酸劑中)의 Ascorbic acid의 안정성(安定性)에 관(關)한 연구(硏究)-)

  • Shin, Sang-Chul;Lee, Min-Hwa;Woo, Chong-Hak
    • Journal of Pharmaceutical Investigation
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    • v.3 no.1_2
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    • pp.34-50
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    • 1973
  • There are many reports on the stability of drugs in powders and tablets. The stabilities of ascorbic acid in the antacid preparations, such as calcium carbonate, magnesium carbonate, magnesium trisilicate, magnesium alumino silicate, and dried aluminum hydroxide gel under various humidities were examined. From the result of the experiment, it was assumed that the concentration of ascorbic acid, the amount of water-vapor sorption, and the physical character of the antacid ingredients were the main factors, influencing the degradation of ascorbic acid. The ascorbic acid, mixed with carbonates, such as calcium carbonate, was degradaded rapidly, while the preparation with dried aluminum hydroxide gel was slightly degraded after 10 days. A 2% ascorbic acid in the prepation was rapidly degraded than 10% ascorbic acid in the preparation.

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An Implementation of Addition.Multiplication and Inversion on GF($2^m$) by Computer (Computer에 의한 GF($2^m$) 상에서 가산, 승산 및 제산의 실행)

  • Yoo, In-Kweon;Kang, Sung-Su;Kim, Heung-Soo
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1195-1198
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    • 1987
  • This paper develops algorithms of element generation, addition, multiplication and inversion based on GF($2^m$). Since these algorithms are implemented by general purpose computer, these are more efficient than the conventional algorithms(Table Lookup, Euclid's Algorithm) in each operation. It is also implied that they can be applied to not only the normally defined elements but the arbitrarily defined ones for constructing multi-valued logic function.

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Image Scaling Algorithm of an Arbitrary Rational Scaling Factor and Its Hardware Architecture (임의의 유리수로 표현되는 스케일링 비율을 지원하는 영상 스케일링 알고리즘과 하드웨어 구조)

  • Park, Hyun-Sang
    • Proceedings of the KAIS Fall Conference
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    • 2009.05a
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    • pp.307-310
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    • 2009
  • 임의의 입력 해상도와 출력 해상도의 비율로 주어지는 영상 축소 스케일러를 구현하려면 축소된 영상에 대한 화소의 좌표를 계산하기 위해서 범용 제산기의 사용이 요구된다. 이 범용 제산기는 매 화소마다 동작해야하기 때문에 처리속도를 높이기 위하여 LUT로 구현되나, LUT의 정밀도에 따라서 하드웨어의 규모가 비대해지는 문제가 야기된다. 본 논문에서는 제산기나 LUT 기반의 제산 연산을 수반하지 않는 영상 축소 알고리즘을 제안한다. 제안한 알고리즘은 비교기와 가산기 만으로 구성되어 있으며, 임의의 유리수로 표현되는 축소 비율을 허용함에도 불구하고, 기존 방식에 비해서 1/10 이하로 하드웨어 규모를 줄이는 것이 가능하다.

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