• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.97-103
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• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• Journal of KIISE
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• v.42 no.10
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• pp.1280-1285
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• 2015

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.13-22
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• 2011

Network Intrusion Detection Systems use regular expression to represent malicious packets and hardware-based pattern matching is required for fast deep packet inspection. Although hardware architectures for implementing constraint repetition operators such as {10} were recently proposed, they have some limitation. In this paper, we propose hardware architecture supporting constraint repetitions of general regular expression sub-patterns with lower logic complexity. The subpatterns supported by the proposed contraint repetition architecture include general regular expression patterns as well as a single character and fixed length patterns. With the proposed building block, we can implement more efficiently regular expression pattern matching hardwares.

• 한국어정보학회:학술대회논문집
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• 2017.10a
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• pp.264-266
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• 2017

본 연구는 리마인더 앱을 위한 효과적인 시간 표현 분석 방법을 제안한다. 시간 표현 분석을 위한 정규식 패턴을 이용하여 사용자 발화 텍스트로부터 시간 정보를 분석하고 시간 표현 유형에 따라 절대적 시간 정보로 변환한다. 제안한 방법은 정규식 패턴을 이용한 시간 표현 분석 기법으로 시스템의 유지 관리가 용이하고 정보량이 많은 패턴과의 매칭을 위해 효과적이다.

• Journal of IKEEE
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• v.22 no.1
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• pp.87-92
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• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.

• Annual Conference on Human and Language Technology
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• 2017.10a
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• pp.264-266
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• 2017

본 연구는 리마인더 앱을 위한 효과적인 시간 표현 분석 방법을 제안한다. 시간 표현 분석을 위한 정규식 패턴을 이용하여 사용자 발화 텍스트로부터 시간 정보를 분석하고 시간 표현 유형에 따라 절대적 시간 정보로 변환한다. 제안한 방법은 정규식 패턴을 이용한 시간 표현 분석 기법으로 시스템의 유지 관리가 용이하고 정보량이 많은 패턴과의 매칭을 위해 효과적이다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.136-138
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• 2004

XML 이 웹 상에서의 정보 표현, 통합, 교환을 위한 표준이 됨에 따라 다양한 XML 질의 언어들이 제안되었으며, World Wide Web Consortium(W3C)은 XQery를 XML 질의 언어의 표준으로 권고하였다. XQuery는 SQL과 유사하게 중첩 질의를 허용하므로, 중첩된 XQuery 질의를 동일한 의미를 가지면서 보다 효율적으로 실행될 수 있는 질의로 변환하는 정규화 규칙들이 제안되었다. 그러나 제안된 정규화 규칙들은 제한적인 형태의 중첩 질의에만 적용되는 문제점을 가지고 있다 특히, FLWR 표현식의 where 절에 있는 중첩을 처리할 수 없다. 본 논문에서는 SQL 질의의 정규화 규칙들을 확장하여 FLWR 표현식의 모든 절에 나타나는 중첩을 처리할 수 있는 XQuery 질의의 정규화 규칙들을 제안한다 이를 위해 먼저, 상관과 집계의 유무에 따라 XQuery 질의의 중첩 유형을 분류하고, 각 유형 별로 정규화 규칙들을 제안한다 다음으로, 중첩된 XQuery 질의에 정규화 규칙들을 적용하는 세부 알고리즘을 제안한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.395-404
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• 2013

A pattern matching algorithm plays an important role in traffic identification and classification based on predefined patterns for intrusion detection and prevention. As attacks become prevalent and complex, current patterns are written using regular expressions, called regexes, which are expressed into the deterministic finite automata(DFA) due to the guaranteed worst-case performance in pattern matching process. Currently, because of the increased complexity of regex patterns and their large number, memory-efficient DFA from states reduction have become the mainstay of pattern matching process. However, most of the previous works have focused on reducing only the number of states on a single automaton, and thus there still exists a state blowup problem under the large number of patterns. To solve the above problem, we propose a new state compression algorithm that merges states on multiple automata. We show that by merging states with the same input character on multiple automata, the proposed algorithm can lead to a significant reduction of the number of states in the original DFA by as much as 40.0% on average.

• Journal of Internet Computing and Services
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• v.2 no.1
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• pp.1-11
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• 2001

Though it is proposed to use Petri net or dynamic FSM methods for the generation of test sequences on some specific protocols, those methods ere unavailable on the cases where the protocol allows faults processing or includes paths in looping which cause errors or endless looping by the explosion of states. The determination of test coverage on the protocol software that has been designed and implemented is difficult by the reason of development periods, technical solutions to support and also economical limitations. It is suggested to generate timely protocol software test sequences on the basis of regular expressions covering the functions of protocol. With this regular expression method, the 38 test sequences of Q.2971 protocol has been generated and also minimized the endless looping problem when dynamic test suites are used by simplifying the test path expressions that denotes loops, According to the works, the suggested method is confirmed as simple and easy compare to the other dynamic test sequence generation techniques. Moreover. the method to search an optional test path whether it Is included or not in the regular path expression is reviewed.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.31-34
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• 2015

현재의 한글 정규식은 완성형 한글에 맞춰 글자단위로 사용할 수밖에 없으므로 사용이 불편하다. 따라서 이러한 불편함을 해결하기 위해 자모단위로 처리 가능한 조합형 한글 정규식 Java 라이브러리를 설계하였다. 조합형 한글 정규식 Java 라이브러리를 통해서 단순히 '가'로 시작하는 글자가 아니라 'ㄱ'으로 시작하는 글자나, 종성이 없는 단어 등을 처리할 수 있으며 기존의 정규식 문법 또한 사용할 수 있다. 이를 위해서 초성, 중성, 종성 각각에 조건을 주는 규칙을 한글 정규식 문법에 추가하였으며, 기존의 Java 정규식 라이브러리와 해당 라이브러리에서 이용하는 유니코드 표현상에서의 한글 인코딩 특징을 이용하였다.