• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.71-82
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• 2004

Recently, network model inspired by social insect behavior attracts the public attention. The AntNet is an adaptive and distributed routing algorithm using mobile agents, called ants, that mimic the activities of social insect. In this paper. we present a new hardware architecture to realize an AntNet-based routing in practical system on a chip application. The modified AntNet algorithm for hardware implementation is compared with the original algorithm on the various traffic patterns and topologies. Implementation results show that the proposed architecture is suitable and efficient to realize adaptive routing based on the AntNet.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.865-872
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• 2017

Recently, in response to the Internet age, the demand for hardware devices has been increasing, centering on the rapidly growing smart home field, due to the growth and management of sensor and control technology, mobile application, network traffic, big data management and cloud computing. In order to maintain the sustainable development of the hardware system, it is necessary to update the system, and the hardware device is absolutely necessary in real time processing of complex data (voice, image, etc.) as well as data collection. In this paper, we propose a method to simplify the control and communication method by integrating the hardware devices in two operating systems in a unified structure to solve the simultaneous control and communication method of hardware under different operating systems. The performance evaluation results of the proposed integrated hardware and the cloud control system connected to the cloud server are described and the main directions to be studied in the field of internet smart home are described.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.3
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• pp.45-55
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• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.

• Journal of IKEEE
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• v.20 no.3
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• pp.241-250
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• 2016

AVM(Around View Monitoring) is a function of ADAS(Advanced Driver Assistance Systems), which provides a bird's eye view of the surroundings of a vehicle to the user. AVM systems require large bandwidth since they are composed of four input images and require real-time processing for vehicle-embedded environments. Also, the memory bandwidth requirement increases greatly when the resolution of the input data is higher. In this paper, we propose four basic hardware models of AVM systems. The models are decided by whether or not there is a valid data extraction module and an image processing purpose LUT generation module. We analyze the required bandwidth and hardware resource for each model. For verification of the proposed models, we implemented an AVM system using XC7Z045 FPGA and DDR3 memory for VGA and FHD resolution. All four of the proposed hardware model is executed below 33ms, which shows that it can operate in real-time.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.32-40
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• 2019

Indoor location estimation studies are needed in various fields. The method of estimating the indoor position can be divided into a method using hardware and a method using no hardware. The use of hardware is more accurate, but has the disadvantage of hardware installation costs. Conversely, the non-hardware method is not costly, but it is less accurate. To estimate the location for AR game, you need to get the solution of the Perspective-N-Point (PnP). To obtain the PnP problem, we need three-dimensional coordinates of the space in which we want to estimate the position and images taken in that space. The position can be estimated through six pairs of two-dimensional coordinates matching the three-dimensional coordinates. To further increase the accuracy of the solution, we proposed the use of an additional non-coplanarity degree to determine which points would increase accuracy. As the non-coplanarity degree increases, the accuracy of the position estimation becomes higher. The advantage of the proposed method is that it can be applied to all existing location estimation methods and that it has higher accuracy than hardware estimation.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.86-94
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• 2012

In this paper we propose a hardware architecture of high-speed CGH (computer generated hologram) generation processor, which particularly reduces the number of memory access times to avoid the bottle-neck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation rather than light source-by-source calculation. The second is parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last one is a fully pipelined calculation scheme and exactly structured timing scheduling by adjusting the hardware. The proposed hardware is structured to calculate a row of a CGH in parallel and each hologram pixel in a row is calculated independently. It consists of input interface, initial parameter calculator, hologram pixel calculators, line buffer, and memory controller. The implemented hardware to calculate a row of a $1,920{\times}1,080$ CGH in parallel uses 168,960 LUTs, 153,944 registers, and 19,212 DSP blocks in an Altera FPGA environment. It can stably operate at 198MHz. Because of the three schemes, the time to access the external memory is reduced to about 1/20,000 of the previous ones at the same calculation speed.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.336-338
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• 1999

전자상거래에 대한 요구가 급증하고 있는 오늘날, 상대방의 신뢰성을 보증해 주는 인증서 사용이 빈번해지고 있다. 기존에는 인증기관이 발급한 인증서를 사용자가 보관하다가, 전자상거래를 할 경우 이를 전자서명과 함께 상대방에게 제시하여 서로의 신뢰성을 확인하였지만, 이 방법은 사용자가 인증서와 비밀키를 자신의 하드웨어 디스크에 보관하거나, 스마트 카드 또는 플로피디스켓에 휴대하고 다녀야 하는 번거로움이 있었다. 사용자의 이동이 많아지고, 사용자가 자신의 위치나 하드웨어 플렛폼에 상관없이 전자상거래를 하고자 하는 요구가 증대됨에 따라서, 인증서와 비밀키를 휴대해야 하는 불편함은 커다란 제약점이라고 할 수 있다. 본 논문에서는 이러한 문제를 극복하고, 사용자가 어느 곳에서든지 웹브라우져를 사용하여 쉽게 인증서와 비밀키를 사용할 수 있도록 하는 웹기반 인증성 및 키과리 시스템의 설계와 구현방법을 제안한다. 제안된 시스템은 사용자가 복잡한 패스워드를 기억하지 못한다는 점과 패스워드가 쉽게 노출될 수 있다는 점을 고려하여 SPEKE에서 제시한 방법을 활용하여 로그인하였고, 시스템에 외부인이 침입할 경우에 대비하여 데이터베이스 안의 중요한 정보들은 암호화하여 저장하도록 하였으며, SSL이 설정되지 않았을 경우에도 안전하게 인증서를 위탁할 수 있도록 사용자와 인증서 관리 시스템은 정보를 암호화하여 통신하도록 한다.