• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.19 no.2
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• pp.183-190
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• 2007

Controlling superheat of indoor units associated with a multi-type heat pump is one of difficult tasks to be addressed. This study suggests a dynamic model of an evaporator based on heat and mass balance. Thermodynamic properties are calculated by a commercial software, Refprop. The model is programmed in MFC Visual C++ for controller interface in real-time mode. The simulation results shows that PI control works for a narrow range of superheat. Beyond the range, the temperature behavior of the refrigerant is quite nonlinear mainly due to phase change. Thus, it is concluded that PI control of superheat has to be supplemented by nonlinear control ideas to avoid saturation and excessive superheat.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.12
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• pp.130-141
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• 2008

This paper presents the flow characteristics in the fluid circulation loop using the tubular type linear induction motor(TLIM) electromagnetic pump. A TLIM of thrust 40[N] is analyzed using the equivalent and genetic algorithm for the system The flow characteristics are analyzed by coupling the Maxwell equations with the Navier-Stokes equation with the thrust. The analysis algorithm is developed for analyzing the liquid metal flow in the system for laminar and turbulent flow. And the effect of thrust is analyzed for the flow characteristics.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• Journal of IKEEE
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• v.23 no.3
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• pp.1061-1067
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• 2019

In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.269-277
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• 1996

The vacuum systems of PLS linac provides average pressure of $2.6\times 10^{-6}$Pa under high power microwave of 54 MW peak with 4.1 $\mu \textrm s$ pulse width and 10 Hz repetition rates. The base pressure of system is$2.4\times 10^{-6}$Pa with 45$^{\circ}C$ cooling water. The outgassing rate of the system is decreased from $3.0\times 10^{-11}Torr-l/sec-\textrm{cm}^2$ at the initial stage after installation to $1\times 10^{-12}Torr-l/sec-\textrm{cm}^2$ at present. Total accumulated microwave energy dose is about 140 GJ per module. All ion pumps are working under saturated regime and effective pumping speeds of 60 I/s, 230 I/s ion pumps are 45 I/s, 65 I/s, 140 I/s under the operating range. Main problems occurred in recent year are troubles of ion pump controller and vacuum gauge controller, vacuum leak of energy doubler window and electron gun ceramic, and water leak in the dummy load of acceleraing columns. Total of 41 troubles with 140. 8 hours down time give good system availability of 98%. Down time can be reduced by high power waveguide valves and water dummy loads under development, and then availability is expected to be increased up to 99.5%.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.1-7
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• 1998

Due to the increase in capacity of auxiliary machinery in power plant, the importance of energy saving has been greatly emphasized. If the speed of fans or pumps is controlled in accordance with the variation of load, large electric energy can be saved. Large capacity inverter, 2MVA GTO inverter, has been developed by operating two of 1MVA unit inverters in parallel. The parallel operation of the unit inverter is accomplished through two output transformers of which the secondary windings are connected in series. The system is composed of one control cubicle, one rectifier cubicle and 2 unit inverter cubicles. This inverter system was applied to the sea water lift pump(SLP) driven by a 6.6KV 1500KW induction motor in Seo-Inchon power plant to save the electric energy. The parallel operation of inverters by 180 degrees apart in switching frequency helps to reduce the harmonic components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.