• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.5
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• pp.394-402
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• 2021

The entry of an aging society and the extension of human life expectancy, the increasing interest in women's social advancement and men's appearance, and the natural interest in K-culture through media media, while receiving worldwide attention, Focus on K-Bueaty. Recently, looking at the occupation of the medical tourism field, in the case of aesthetic medicine tourism such as molding and dermatology, it has gained popularity not only in Asia such as China and Japan, but also in North America and Europe. The first external confirmation of human aging is the wrinkles on the skin of the face. Clean, wrinkle-free, elastic and healthy skin is a desire of most people. Skin condition and condition such as focused ultrasonic stimulation (HIFU: High Intensity Focused Utrasound) and low frequency, high frequency (RF: Radio Frequency), galvanic therapy using microcurrent, cryotherapy using rapid cooling, etc. Depending on the method of management, the effect of the treatment differs depending on the output and the stimulation site, etc., even in the treatment of medical equipment and beauty equipment using the same mechanism. In this research, in order to develop invasive high-frequency dermatological devices using a large number of beauty medical devices and microneedles of beauty devices, the international standards IEC 60601-2 (standards for individual medical devices) and MFDS (Ministry of) We designed and developed a high-frequency output device in compliance with the high-frequency stimulation standard announced in the Food and Drug Safety (Ministry of Food and Drug Safety). The circuit design consists of an amplifier (AMP: Amplifier) using Class-A Topology and a power supply device using Half-Bridge Topology. As a result of measuring the developed high-frequency output device, an average efficiency of 63.86% was obtained, and the maximum output was measured at 116.7W and 50.67dBm.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

• Journal of IKEEE
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• v.23 no.4
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• pp.1461-1464
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• 2019

In this paper, we propose the development of embedded board for integrated radiation exposure protection fireman's life-saving alarm capable of location tracking and radiation measurement. The proposed techniques consist of signal processing unit, communication unit, power unit, main control unit. Signal processing units apply shielding design, noise reduction technology and electromagnetic wave subtraction technology. The communication unit is designed to communicate using the wifi method. In the main control unit, power consumption is reduced to a minimum, and a high performance system is formed through small, high density and low heat generation. The proposed techniques are equipment operated by exposure to poor conditions, such as disaster and fire sites, so they are designed and manufactured for external appearance considering waterproof and thermal endurance. The proposed techniques were tested by an authorized testing agency to determine the effectiveness of embedded board. The waterproof grade has achieved the IP67 rating, which can maintain stable performance even when flooded with water at the disaster site due to the nature of the fireman's equipment. The operating temperature was measured in the range of -10℃ to 50℃ to cope with a wide range of environmental changes at the disaster site. The battery life was measured to be available 144 hours after a single charge to cope with emergency disasters such as a collapse accident. The maximum communication distance, including the PCB, was measured to operate at 54.2 meters, a range wider than the existing 50 meters, at a straight line with the command-and-control vehicle in the event of a disaster. Therefore, the effectiveness of embedded board for embedded board for integrated radiation exposure protection fireman's life-saving alarm has been demonstrated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of The Korean Association For Science Education
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• v.35 no.6
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• pp.939-947
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• 2015

For secondary school teachers who attended 'A Social Constructionism Science Teacher Training Program', we analyzed their processes of cognizance change as well as whether they put its results into practice in the field of education, so as to find out the efficacy of the program. 'A Social Constructionism Science Teacher Training Program' consists of three phases based on La main ${\grave{a}}$ la $p{\hat{a}}te$, a French experience-oriented science education program. In its first phase, a study of the philosophy of La main ${\grave{a}}$ la $p{\hat{a}}te$ was made, together with a search for examples of creativity education. In its second and third stages, real education programs were developed for designated themes and free themes, respectively, and then discussions were made. It was a ten-session program, with each session comprising a four-hour sub-program. All activities were both visually and orally recorded, while the participants were asked to write reflective journals for each class. An additional survey and interview were conducted six months later to check if the seven selected secondary school teachers put the results of the program into practice. It was found that changes may be made in the beliefs of teachers with the introduction of theories in teacher indoctrination, but the acquisition of practical knowledge that can be implemented in actual classes may be effectively secured by demonstrations and practice sessions. It was concluded that indoctrination should be conducted to lead participants to the level of practical planning from the level of mere belief so that the theories might actually be put into practice in the education field.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.15 no.1
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• pp.41-50
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• 2010

We have developed an in-situ benthic chamber (BelcI) for use in coastal studies that can be deployed from a small boat. It is expected that BelcI will be useful in studying the benthic boundary layer because of its flexibility. BelcI is divided into three main areas: 1) frame and body chamber, 2) water sampler, and 3) stirring devices, electric controller, and data acquisition technology. To maximize in-situ use, the frame is constructed from two layers that consist of square cells. All electronic parts (motor controller, pA meter, data acquisition, etc.) are low-power consumers so that the external power supply can be safely removed from the system. The hydrodynamics of BelcI, measured by PIV (particle image velocimetry), show a typical "radial-flow impeller" pattern. Mixing time of water in the chamber is about 30 s, and shear velocity ($u^*$) near the bottom layer was calculated at $0.32\;cm\;s^{-1}$. Measurements of diffusivity boundary layer thickness showed a range of $180-230\;{\mu}m$. Sediment oxygen consumption rate, measured in-situ，was $84\;mmol\;O_2\;m^{-2}\;d_{-1}$, more than two times higher than on-board incubation results. Benthic fluxes assessed from in-situ incubation were estimated as follows: nitrate + nitrite = $0.18\;{\pm}\;0.07\;mmol\;m^{-2}\;d^{-1}$ ammonium $23\;{\pm}\;1\;mmol\;m^{-2}\;d^{-1}$ phosphate = $0.09\;{\pm}\;0.02\;mmol\;m^{-2}\;d^{-1}$ and silicate = $23\;{\pm}\;1\;mmol\;m^{-2}\;d^{-1}$.