• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.51-51
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• 2009

Thin Cross 초음파모터의 구조는 그림 1(a)와 같이 크로스형태의 얇은 스테이터에 윗면과 아랫면에 각각 8개의 압전세라믹이 부착된 형태이다. 압전세라믹의 분극방향은 로터와 접촉하는 스테이터의 중심부인 네 개의 타 점에서 순차적인 타원변위가 생성되도록 결정된다. 유한요소해석프로그램인 ATILA 5.2.4를 사용하여 최적설계된 모델을 제작하였고, 푸쉬풀 게이지, x-y 스테이지, rpm 메타, 토크 게이지를 이용하여 구동시스템을 구성하였다. 그림 1(b)는 마이크로컨트롤러(ATmega)를 이용한 구동 드라이버를 보여준다. 한 주기에서 1/4분주의 순차적인 네 개 의 구형파를 생성하고, 이를 push-pull회로를 통하여 90도의 위상차가 나는 정현파를 생성하여 초음파 모터의 구동 전원으로 사용한다. 피드백 회로인 맨코더와 AD 컨버터는 정속도 운전을 위해서 사용되었다. 제안된 구동드라이버를 이용하여 측정한 결과, 기존의 제품화된 드라이버와 비교하여도 특성의 큰 차이를 보이지 않았으며 피드백 회로를 통하여 부하변화에 따른 속도의 극심한 변화를 비교적 안정화 시킬 수 있었다. 입력전압을 증가시킬수록 속도는 선형적인 증가를 보였고 토크는 이와 반대로 감소하는 특성을 보였다. 피드백 제어회로가 없는 경우에는 프리로드 변화에 따른 극심한 속도 변화를 보였고, 피드백 제어를 하였을 경우에는 0.2~0.4[N]의 범위에서 정속도 운전이 가능함을 확인하였으며, 장시간의 운전에도 온도 및 속도특성이 안정적인 특성을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.65-72
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65${\mu}m$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mV ant 200MHz sampling frequency and the input offset is improved about 80% compared with previous work in $5k{\Omega}$ input resistance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.869-872
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• 2005

This paper presents a new switchable dual mode VCO(Voltage-Controlled Oscillator). The VCO is efficient in dual mode operation and has self-bias adjustment based on the operation frequencies of 2.4 GHz and 5 GHz. The switching is done using MOS transistors and tuning is done using MOS varactors. It is implemented using TSMC 0.18${\mu}$m CMOS technology. It is powered by 1.8V supply. The measured results showed that the overall tuning range is approximately 13% at 5 GHz and 8% at 2.4 GHz. The measured phase noise is approximately -102 dBc/Hz at 1 MHz offset for 5 GHz and -89 dBc/Hz at 600kHz offset for 2.4 GHz. The VCO showed tail currents of 2mA in 5GHz mode and 2.5mA in 2.4GHz mode from a 1.8 V supply, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.12
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• pp.8306-8313
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• 2015

Open-type current sensors have been commonly used for DC motor controller, AC variable controller and Uninterruptible Power Supply. Recently they have begun to be used more widely, as the growth of renewable energy and smart-grid in power system. Considering most of the open-type current sensors are imported, developing the core technology needed to produce open-type current sensors is required. This paper describes the development and test results of open-type current sensors. Design of C type magnetic core, selection and test of a Hall sensor, design of current source circuit and signal conditioning circuit are described. 100A class DIP(Dual In-line Package) type and SMD(Surface Mount Devide) type open-type current sensors was made and tested. Test results show that the developed open-type current sensor satisfies the accuracy requirement of 2% and linearity requirement of 2% at 100 A of DC and AC current of 60Hz. Temperature compensation was carried out by using a temperature compensation circuit with NTC(Negative Temperature Coefficient) thermistor and the effect of the temperature compensation are described.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Journal of the Korea Institute of Military Science and Technology
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• v.11 no.5
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• pp.5-11
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• 2008

Recently developed radars use the solid-state power amplifier to amplify the RF signal. The stability of RF signal directly depends on that of the electric power. So the stable and reliable electric power should be needed. When the electric power switch is tuned on for the first time in order to operate the radar system, the in-rush current is generated because of the capacitive characteristic. The excess in-rush current breaks the element. Therefore, the analysis about the in-rush current to design the electric power system is necessary. In this paper, modeling and simulation on the whole power system is carried out and the necessity of limiting the in-rush current is verified. After the analysis, the circuit to limit the in-rush current is designed and examined to verify the analysis. The circuit is good enough to limit the in-rush current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.77-82
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• 2006

Analog channel selection filter is described which is designed for a direct-conversion receiver of a IEEE 802.11a wireless LAN. The channel selection filter is an active-RC fifth-order Chebyshev filter with 10MHz cut-off frequency. Two-stage operational amplifier of the filter employs a current re-using feedforward frequency compensation scheme to minimize the power consumption. The filter has been implemented in a 0.18mm CMOS technology and the experimental results show 20mW power consumption with 1.8V supply voltage and 19dB out-of-band iIP3.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.6 s.312
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• pp.33-39
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• 2006

Trichromatic LED backlight renders higher colour gamut and panel transmittance to the LCDs than the phosphor-converted white LED backlight. In realization, however, several technical challenges arise, such as colour shift, due to the ambient temperature change, brightness decrease along with the temperature increase, colour mixing, minimizing the total number of chips and so on. In this paper we designed and tested the low cost temperature compensating circuit, using a thermistor as a temperature compensating element, for stabilizing the brightness and maintaining the colour coordinates of the trichromatic backlight units. By applying the temperature compensating circuit, the decrement rate of the brightness and colour shift rate were achieved by 54% and 51% respectively comparing with uncompensated case.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.6
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• pp.610-619
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• 2000

This paper presents an off-line UPS using the high temperature superconductive magnetic bearing. FES(Flywheel Energy Storage) system has good advantages in compare with lead acid battery. So, high efficiency FES using high temperature SMB(superconductive magnetic bearing) was composed in this paper. The outer rotor type of PMSM(Permanent Magnet Synchronous Motor) as motor/generator was used for the experiment, and square wave current and sinusoidal wave control methods was compared for high efficiency operation of motor/generator. The circuit for in phase sinusoidal wave current control with EMF in the full speed range was designed and the proposed flywheel energy storage system was applied in single phase off-line UPS system. As the stable operation characteristics of prototype system was confirmed, the its excellence as energy storage device in Off-line UPS was proved.