• Journal of Advanced Navigation Technology
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• v.22 no.6
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• pp.654-664
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• 2018

In this paper, this system is operated by PCS that is driven by being synchronized voltage fed inverter and AC source, and in the steady state of power source charge battery connected to DC side with solar cell using a photovoltaic (PV) that it was so called constant voltage charge. it can cause the effect of energy saving of electric power, from 10 to 20%. and through a normal operation of electric energy storage system (EESS). In addition, better output waveform was generated because of pulse width modulation (PWM) method, and it was Proved to test by experiment maintained constant output voltage regardless of AC source disconnection, load variation, and voltage variation of AC power source.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.724-726
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• 2002

개인이동기기의 사용이 증가함에 따라, 보다 효율적이고 편리한 이동시스템을 위한 많은 연구가 진행되고 있다. 특히 에너지 소모의 절감에 대한 연구는 이동기기의 기동성을 위해 중요한 문제이다. 동적전압조정은 이동기기의 에너지 소모를 가장 많이 차지하는 요소 중 하나인 프로세서의 전력을 효율적으로 관리하고 감소시킬 수 있는 방법이다. 본 논문에서는 MPEG 프레임별 복호시간의 차이를 이용한 동적전압조정 알고리듬을 통해 프로세서가 WPEG디코더를 실행할 때 전력소모를 최소화하는 과정을 프로세서 시뮬레이터를 통해 확인한다. 논문에서 제안한 동적전압조정 알고리듬은 원래의 프로세서 에너지 소모와 비교하여 약 70%-85%의 감소효과를 볼 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.408-408
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• 2012

반세기가 지나는 동안 우리는 반도체의 크기가 계속해서 작아지는 것을 경험해왔다. 반도체 디바이스들의 차원이 100 nm 이하로 작아지면서, 나노와이어나 나노튜브로 이루어진 나노 소자들은 필연적으로 양자효과[1] 같은 저차원효과가 나타나게 된다. 특히 1차원 반도체 구조에서는 전자상태 밀도의 변화에 수반되는 전자-포논의 상호작용이 감소되어 전자이동도가 증가할 것으로 예측되었고, 이러한 이동도의 증가는 그동안 나노와이어나 나노튜브의 전기 전도도 증가가 일어난 실험적 데이터를 설명하는 이론적 받침이 되었다[2]. 한편 일차원 반도체 구조 체에서는 채널의 저차원화에 따른 전기장의 불균일성이 심화되고 이로 인하여 벌크와 매우 다른 전기수송 특성이 나타날 수 있는데 이러한 점이 그동안 간과되어 왔다. 본 연구에서는 시뮬레이션을 통하여 양자효과를 배제한 정전기적인 저차원 효과만으로도 전기 전도도가 증가할 수 있음을 보이고자 한다. 우리는 푸아송 방정식과 표동-확산 방정식을 SILVACO사의 ATLAS 3D 시뮬레이터를 이용하여 풀었다. 이 시뮬레이션에 사용된 실리콘 나노와이어는 길이를 $2{\mu}m$로 고정시키고 다양한 정사각형 단면적을 가진 구조로 하였다. 여기서 정사각형의 한변을 10nm 에서 100 nm까지 변화시켰다. 실리콘 채널의 도핑농도가 $1{{\times}}1016cm-3$일 경우, 낮은 전압, 즉 < 0.5 V 이하 영역에서는 벌크와 같은 선형적인 전류-전압 특성이 나타나지만, 그 이상의 전압 영역에서는 전류-전압 그래프가 위로 휘어지며(super-linear) 전기전도도가 확연히 증가함을 알 수 있었다. 예를 들어 2 V에서는 벌크에 비하여 흐르는 전류가 2배나 더 향상되었다. 이런 비선형적인 성질은 높은 전압을 인가하였을 때 나노와이어 채널 전반에 걸쳐 charge neutrality가 깨지게 되고 전하밀도가 증가하여 전도도 증가가 일어나는 것으로 밝혀졌다. 이 결과는 기존의 나노선에서의 전기전도도 증가 현상을 설명할 수 있는 대안을 제공할 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.731-733
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• 2012

Because the Double gate MOSFET has two gates, it has more efficient on controling current than the exisiting MOSFET, and it can also decrease short channel effects in the nano-device. In this study, during the manufacturing the Double gate MOSFET, we will analyze the change of threshold voltage according to doping concentration that makes a significant impact on short channel effects. One of the structural factors that affect the threshold voltage on the Double gate MOSFET is the doping concentration, and it is very important device parameter. In this paper, we can find that the threshold voltage became larger when the doping concentration increased from $10^{15}cm^{-3}$ to $10^{19}cm^{-3}$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.10
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• pp.5148-5155
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• 2013

The induced voltage on the telecommunication cable generated by nearby electric railway system may bring about telecommunication errors and safety accidents. In order to reduce the induced voltage and to achieve communication reliability, the effect of the shield cables and the recent double-track railway systems on the inductive interference should be investigated. This paper analyzes the parameters which seriously influence the induced voltage on the telecommunication cables which run parallel with a AT-fed electric railway line, and provides a simulation-based approach to estimate the amount of the induced voltage. Simulation results indicate that the induced noise voltage generated by a double-track railway decreases by 18 % compared to that generated by a single-track railway, showing the screening effect by nearby track. The induced noise voltages on the 50%-shielded cable and 15%-shielded cable decrease to 1/8 and 1/15 of the induced voltage on the non-shielded cable, respectively. A meaningful shield effect is achieved and the induced voltage is minimized by the double-track railway and the shielded cable.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.848-851
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• 2012

In this paper, circuit of reducing the offset voltage in Op-amp, effectively, is newly proposed by using dual capacitor. Capacitors and MOS switches are added in proposed circuit to make up for the weak points of previous circuits ofr reducing the offset voltage in auto-zeroing method. Also, it is designed to reduce the offset voltage in high frequency range by using chopping method, effectively. Circuit simulation and layout are executed by TSMC 1.8V, 0.18um process. From the simulation results, it is verified that magnitude of offset voltage is under 5mV and proposed circuit is good for compensation of offset voltage better than previous auto-zeroing method.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.180-182
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• 2019

본 논문에서는 옵셋 전압을 이용한 3레벨 인버터의 불연속 PWM 방법을 제안한다. 스위칭 상태에 따른 3레벨 인버터의 출력전압을 벡터공간에서 도시하여 전압 변조 지수에 따른 DC 레일 및 중성단 클램핑 가능 영역을 분석한다. 이를 바탕으로, 3상 전압 지령 크기를 입력으로 받아 중성단의 클램핑 가능 여부를 판별하고 원하는 지점으로 클램핑 시켜주는 옵셋 전압 생성부를 제안한다. 제안된 방법은 공간 벡터 전압 변조 방식에 비해 간단하며, 기존 2레벨 인버터의 불연속 PWM 방식을 기반으로 하므로 구현에 용이하다. 시뮬레이션 및 실험으로 이론의 타당성 및 효과를 검증하였다.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.47-52
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• 2017

This research scrutinizes the data retention characteristics of the MLC NAND Flash Memory instigated by the loss effect of trapped charge when the memory is in the state of program saturation. It is attributed to the threshold voltage saturation phenomenon which engenders an interruption to the linear increase of the voltage in the memory cell. This phenomenon is occasioned by the outflow of the trapped charge from the floating gate to the control gate, which has been programmed by the ISPP (Incremental Step Pulse Programming), via Inter-Poly Dielectric (IPD). This study stipulates the significant degradation of thermal retention characteristics of threshold voltage in the saturation region in contrast to the ones in the linear region. Thus the current study evaluates the data retention characteristics of voltage after the program with a repeated reading test in various measurement conditions. The loss effect of trapped charge is found in the IPD layer located between the floating gate and the control gate especially in the nitride layer of the IPD. After the thermal stress, the trapped charge is de-trapped and displays the impediment of the characteristic of reliability. To increase the threshold saturation voltage in the NAND Flash Memory, the storage ability of the charge in the floating gate must be enhanced with a well-thought-out designing of the module in the IPD layer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.672-677
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• 2013

This paper have analyzed the change of breakdown voltage for channel dimension of double gate(DG) MOSFET. The breakdown voltage to have the small value among the short channel effects of DGMOSFET to be next-generation devices have to be precisely analyzed. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The breakdown voltages have been analyzed for device parameters such as channel thickness and doping concentration, and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result, we know the breakdown voltage is influenced on Gaussian function and device parameters for DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.811-814
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• 2012

This paper have analyzed the change of breakdown voltage for channel dimension of double gate(DG) MOSFET. The breakdown voltage to have the small value among the short channel effects of DGMOSFET to be next-generation devices have to be precisely analyzed. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The breakdown voltages have been analyzed for device parameters such as channel thickness and doping concentration, and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. Resultly, we know the breakdown voltage is influenced on Gaussian function and device parameters for DGMOSFET.