• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.11
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• pp.817-825
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• 2017

The AC-common bus microgrid system can overcome several weaknesses of the DC microgrid system by interconnecting the DC/AC inverters used for renewable energy with an AC network. Nevertheless, the unbalanced loads inherent in the electric power systems of island and small communities can deteriorate the performance of the AC microgrid system. This is because of the limited voltage regulation capability and mixed power flow in the voltage source inverter. In order to overcome the unbalanced load condition, this paper proposes a voltage and current control algorithm for the 4-leg inverter based on the single phase d-q control method, as well as the modeling of the voltage controller using Matlab/Simulink S/W. From the S/W simulation and experiment of the 250KW proto-type inverter, it is confirmed that the proposed algorithm is a useful tool for the design and operation of the AC microgrid system.

• Food Science of Animal Resources
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• v.23 no.1
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• pp.28-31
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• 2003

The incidence of PSE pork by lairage time, use of electric probe, stunning voltage condition and carcass chilling rate was compared. The incidence of PSE pork was 22.2% when pigs were held in lairage overnight without electric probe, whereas it was 59.3% when held in lairage for < 1.5 hr with electric probe before slaughter. The incidence of PSE pork was 42.37% when pigs were treated with 230 V of stunning condition, and was 66.67% when treated with 500V of stunning condition. The incidence of PSE pork was 52.2% when the ultimate carcass internal temperature was controlled higher than 38$^{\circ}C$ with the slow chilling(-5$^{\circ}C$ for 70 min), and was 39.6% when controlled lower than 30$^{\circ}C$ with the fast chilling(-15$^{\circ}C$ for 70 min). Results indicated that the incidence of PSE pork was decreased by 37.1% with lairage overnight and without use of electric probe, 24.3% with low voltage stunning treatment and 12.6% with fast chilling. However, the incidence of PSE pork was not significantly correlated with carcass weight.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.11
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• pp.981-987
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• 2014

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a MOSFET (metal-oxide semiconductor field effect transistor), a PWM-IC (pulse width modulation-integrated circuit) controller, inductor, capacitor, etc. It is shown that the variation of threshold voltage and the breakdown voltage in the electrical characteristics of MOSFET occurs by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 5 heavy ions make the gate of MOSFET broken in SEGR (Single Event Gate Rupture) testing. TID testing on MOSFET is accomplished up to the total dose of 40 krad, and the cross section($cm^2$) versus LET(MeV/mg/$cm^2$) in the MOSFET operation is studied at SEGR testing after implementation of the controller board.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.11-19
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• 2004

A software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software, is usually used for LEO satellites. This paper proposes a new power-stage circuit that can be available for modularization of a power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of the proposed power-stage and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stage.

• Journal of IKEEE
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• v.24 no.1
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• pp.216-224
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• 2020

This paper proposes an impedance design method of the test device for evaluating Low Voltage Ride Through(LVRT) and High Voltage Ride Through(HVRT) functions. The LVRT/HVRT test device should have ability to generate the fault voltage specified in the grid code for a certain period and to limit the magnitude of the fault current with the design specification. In this paper, the impedance design method for auto transformer is proposed based on a equivalent model of a tap-change auto-transformer during LVRT/HVRT operation. In addition, to generate various fault voltages required the LVRT/HVRT test, tap impedance design in the auto transformer is considered. To verify the validity of the proposed design method, the design process of the 10MVA LVRT/HVRT test device was conducted and the design results was verified through simulation models.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.3
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• pp.264-272
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• 2009

In this paper, a Ka-band 10 W power amplifier module is designed and fabricated using MIC(Microwave Integrated Circuit) module technology which combines multiple power MMIC(Monolithic Microwave Integrated Circuit) chips on a thin film substrate. Modified Wilkinson power dividers/combiners are used for millimeter wave modules and CBFGC-PW-Microstrip transitions are utilized for reducing connection loss and suppressing resonance in the high-gain and high-power modules. The power amplifier module consists of seven MMIC chips and operates in a pulsed mode. for the pulsed mode operation, a gate pulse control circuit supplying the control voltage pulses to MMIC chips is designed and applied. The fabricated power amplifier module shows a power gain of about 58 dB and a saturated output power of 39.6 dBm at a center frequency of the interested frequency band.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Journal of IKEEE
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• v.23 no.3
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• pp.947-953
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• 2019

The purpose of this paper is to explore an ASIC design for estimating sizes and concentrations of airborne micro-particles by the means of integrating, amplifying and digitizing electric charge signals generated by photo-sensors as it receives scattered photons by the presence of micro-particles, consisting of a pre-amplifier that detects and amplifies voltage or current signal from photo-sensor that generates charges (hole-electron pairs) when exposed to visible rays, infrared rays, ultraviolet rays, etc. according to the intensity of rays; a shaper for shaping the amplified signal to a semi-gaussian waveform; two discriminators and binary counters for outputting digital signals by comparing the magnitude of the shaped signal with an arbitrary reference voltages. The ASIC with the proposed architecture and functional blocks in this study was designed with a 0.18um standard CMOS technology from Global Foundries and the operation and performances of the ASIC has been verified by the silicons fabricated by using the process.