• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.820-825
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• 2004

In this paper an octave tuning voltage controlled oscillator which is used in set-top TV tuner was designed. Oscillation frequency range is 0.9 GHz～2.2 GHz with 1.3 GHz bandwidth. By using 4 varactor diodes in base and emitter of transistor, wide-band tuning, sweep linearity and low phase noise could be achieved. Designed VCO requires a tuning voltage of 0 V ～ 20 V and DC consumption of 10 V and 15 mA. Designed VCO exhibits an output power of 5.3 dBm $\pm$1.1 dB and a phase noise below -94.8 dBc/Hz ＠ 10 kHz over the entire frequency range. The sweep linearity shows 65 MHz/V with a deviation of $\pm$10 MHz.

• The Magazine of the IEIE
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• v.24 no.1
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• pp.38-46
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• 1997

최근 몇 년 동안 이동통신에 대한 시장 규모는 급성장을 보여왔다. 이러한 시장규모 성장에 힘입어 단말기에 사용되는 RF부품 제작 기술 또한 급진전됐으며 이동통신용 RF부품은 과거에 비해 놀라울 정도로 소형 경량화 되어 단말기의 휴대성을 더욱 높이고 있다. 특히 전압 제어 발진기의 경우 지난 10년 사이에 1/30 정도로 크기가 축소 됐으며 향후로도 계속적으로 축소되어 좀더 휴대하기 간편하고 편리한 다 기능의 단말기를 가능하게 할 것이다. 본 고에서는 과거 10년 동안의 전압제어발진기의 발전동향 및 추세를 살펴보고 현재 사용되는 전압제어 발진기의 구조 및 회로 동작 원리를 설명하고자 한다. 또한 향후 계속되어야 할 전압제어 발진기의 발전 방향을 전망해 보고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1538-1543
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• 2013

In this paper, a novel split ring resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator. Oscillator using proposed split ring resonator is designed, it has improved phase noise characteristics. At the fundamental frequency of 5.8GHz, 7.22dBm output power and -83.5 dBc@100kHz phase noise have been measured for oscillator with split ring resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}/4$ microstrip resonator. Next, we designed voltage controlled oscillator using proposed split ring resonator with varactor diode. The VCO has 125MHz tuning range from 5.833GHz to 5.845GHz, and phase noise characteristic is -118~-115.5 dBc/Hz@100KHz. Due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.767-770
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• 2003

A SiGe HBT MMIC differential VCO has been developed for C-band wireless LAN applications. The VCO produces -6.4 dBm output power at 4.75 GHz. The VCO exhibits a 490 MHz tuning range with control voltage from 0.5 V to 2.5 V. The phase noise of the VCO exhibits -106.5 dBc/Hz at 1 MHz offset from the 4.75 GHz carrier. The total current consumption of the VCO is 10 mA at a supply voltage of 3 V.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.179-182
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• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.699-702
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• 2012

본 논문에서는 WCDMA(Wide Code Division Multiple Access) 시스템 사양을 만족시키는 주파수 합성기 블록 중 위상잡음 및 전력소모의 최적 설계가 필요한 LC-VCO(voltage controlled oscillator)의 설계를 제안 하였다. 최적 설계를 위한 핵심내용은 LC-tank의 손실성분을 보상하는 MOS트랜지스터의 전달컨덕턴스와 인덕턴스 평면에 여유이득라인과 튜닝 범위 라인을 그어 설계 가능한 영역 내에서 위상잡음이 최소가 되는 인덕턴스 값을 구하고 선택하는 것이다. 제안한 최적 설계방법에 의해 진행된 LC-VCO의 시뮬레이션 결과 위상잡음 특성은 1MHz옵셋에서 -113dBc/Hz였다.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2064-2066
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• 2004

본 논문에서는 새로운 개념인 능동 고조파 결합을 이용한 4위상 전압제어 발진기를 설계, 제작하였다. 4위상 출력 특성을 얻기 위하여 각각의 차동 VCO의 가상 접지(Virtual Ground)면을 본 논문에 제시된 능동 고조파 결합 회로(Active super harmonic coupling)을 이용하여 결합시키는 방법을 적용하였다. 제안된 구조는 다음과 같은 장점을 가지고 있다. 결합구조를 갖는 트랜지스터에 부가적인 전류소비를 줄일 수 있으며, layout상에서 문제되었던 대칭구조를 개선할 수 있다. 또한 기존에 발표되었던 방법인 passive transformer를 이용한 고조파 결합 보다 회로 크기를 줄일 수 있다. 측정결과 출력 전력 -12dBm, -117dBc/Hz @1-MHz 이하의 위상잡음 특성, 2.66GHz${\sim}$2.91GHz의 250 MHz 주파수 가변, 25dB이하의 2차고조파 억압, 7 mA 의 전류 소모(buffer amp. 포함되지 않음)를 가졌다.