• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1119-1124
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• 2011

The operation of current conveyor circuit is similar to an operational amplifier and a current conveyor circuit has the characteristics such as good linearity and stability. In this paper, a frequency-to-voltage converter circuit is designed by using a current conveyor circuit. The supply voltage is 5volts and the designed circuit is simulated by HSPICE. The range of the input frequency is from 4kHz to 200kHz. From the simulation results the error of the output voltages is less than from -1.3% to +2.5% compared to the calculated values.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.891-896
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• 2011

This paper describes the differential voltage-to-frequency converter which is realized current conveyor circuits. The output frequency of the differential voltage-to-frequency converter is proportional to the difference of two input voltages. The designed circuit is simulated by HSPICE. The range of input voltage difference is from several volts to several milli-volts. From the simulation results the error is less than from -1.9% to +1.8% compared to the calculated values.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.522-523
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• 2017

Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

• Journal of IKEEE
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• v.23 no.2
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• pp.636-641
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• 2019

A simple resistance deviation-to-time period converter is proposed for interfacing resistive half-bridge sensors. It consists of two 2nd generation current conveyors(CCIIs). The proposed converter has simpler circuit configuration than the conventional converters using operational amplifiers or operational transconductance amplifiers(OTAs). The proposed converter was simulated using CCII implemented with AD844 IC chips. The simulation results show that the converter has a conversion sensitivity of $0.01934ms/{\Omega}$ over a range of $100-500{\Omega}$ resistance deviations and a linearity error less than ${\pm}0.002%$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.80-87
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• 2013

A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2933-2938
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• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.885-890
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• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.32-32
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• 2012

화석연료의 남용으로 지구 온난화가 심화되어 환경과 생태계변화가 가속화되고 있고, 급속한 산업의 발달과 인류 삶의 질 향상에 따른 에너지 수요가 급증하고 있는 실정에 있으며, 일본 후쿠시마 원전사태로 원자력 에너지의 위험성으로 지구 인류환경은 심각한 국면을 맞이 하고 있어 대체 에너지의 하나로 핵융합 에너지 필요성이 증대되고 있다. 핵융합 에너지 연구 개발은 우리나라에서 KSTAR가 1997년부터 건설하기 시작하여 지난 2007년에 완공되어 지금 운용 중에 있고, 국제적으로 미국, EU, 러시아, 중국, 한국, 일본 인도가 참여하는 ITER 국제 공동프로젝트가 2004년에 건설을 시작하여 프랑스 카다라쉬에 실증 플란트를 건설 중에 있다. 이러한 핵융합 반응을 위해서는 10e-7이상의 높은 진공과 1억$^{\circ}C$ 이상에서 중수소와 삼중수소가 반응하여 발생하는 플라즈마를 제어 할 필요가 있으며, 초고온의 핵융합 플라즈마를 가두고 가동시키기 위해서는 약 12Tesla이상의 고자장 마그넷이 필요하다. 현재 ITER 실증 플란트에 사용되는 고자장 마그넷은 TF (Toroidal Field)코일과 CS (Central Field)코일에 Nb3Sn 초전도선재가 핵심부품으로 사용되고 있으며 ITER프로젝트에서는 약 850톤의 Nb3Sn 초전도선재가 사용될 전망이다. 그 중에서 일본 25%, EU, 러시아와 한국이 각각 20%, 중국7%, 미국8% 할당되어 참여국 대부분은 초전도선재를 전략적으로 공급하고 있다. 초전도 선재의 크롬도금은 1~2 마이크로미터 이하의 균일하고 얇은 도금 두께와 밀착성이 우수한 품질이 요구된다. 일반적으로 크롬도금은 산업현장에서 컨베이어 벨트 방식으로 장식이나, 내식성 및 내마모성의 특성을 필요로 할 때 사용되고 있으나, 선재에 크롬도금을 릴투릴(Reel to Reel) 방식으로 적용되는 경우는 세계적으로 아주 드물다. 핵융합 마그넷의 CICC(Conduct In Cable Conduit)도체를 만들기 위해서는 초전도선재를 이용, 3(Sc 2+OFC 1)$^*3^*5^*5^*6$형태로 연선과 케이블링을 하게 되며, 초전도 선재를 연선하고 케이블링을 할 때 크롬 도금층이 박리될 가능성이 있어 크롬도금 방법과 프로세스를 특별히 고안할 필요가 있다. ITER핵융합로 마그넷의 TF코일은 높이 14m, 폭 9m 최대자장 12Tesla, 최대전류 68kA, CICC도체 직경이 40mm로서 그 초전도 조관/도체 내부에 0.82mm 직경의 Nb3Sn 초전도 선재가 약 1350가닥으로 연선과 케이블링으로 구성되어 있다. ITER 핵융합 마그넷용 초전도 선재의 크롬도금은 마그넷 권선 후 Nb3Sn 초전도물질을 형성하기 위해서 $650^{\circ}C$에서 500시간 열처리를 실시하며 열처리 시 초전도 선재의 소선들 사이에 발생할 수 있는 소착을 방지하고, 초전도 선재에서 발생하는 AC loss를 감소시키며, Quench시 발생되는 열을 쉽게 확산시킴으로써, 초전도 마그넷의 열적 안정성(Thermal Stability) 향상과 필요에 따라서 소선간 통전울 가능하게 한다. 고려제강의 자회사인 케이에이티는 크롬도금 밀착성이 우수하고 도금두께 0.1마이크로 미터 이내 제어가 가능한 얇고 균일한 도금품질을 개발하여 한국형 핵융합 실험로인 KSTAR에 65톤 전량 공급하였고, 크롬 도금된 무산소동 선재 32톤과 초전도 선재 93톤을 전량 ITER 프로젝트에 공급하고 있으며, 2013년도 상반기에는 공급을 마무리할 예정이다.