• 한국ITS학회:학술대회논문집
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• 2010.05a
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• pp.87-91
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• 2010

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1059-1066
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• 2005

This paper reports an application of Doherty amplifier for efficiency improvement of feedforward power amplifier(FPA). For performance analysis, we measured 15 W average output power using WCDMA 4FA input signal with a center frequency 2.14 GHz. The applied Doherty amplifier presents the characteristics of high efficiency and low linearity in comparison to the class AB amplifier, and it was used as main amplifier of FPA fir efficiency improvement. To analyze the change of characteristic, tow Doherty amplifiers whose linearity and efficiency are different were applied. The applied FPAs are improved about $2\%$ or more performance in efficiency, but decreased in linearity on 15 W average output power. We additionally modified the coupling factor(CF) of the error loop and the error amplifier capacity for linearity improvement. Aa a result, the efficiency improvement and high linearity resulted from the change of CF and error amplifier capacity. However, we think if the linearity of Doherty amplifier were more than 35 dBc, the FPA would improve the performance about $2\%$ or more efficiency and maintain enough linearity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.114-121
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• 2003

In this paper, low voltage and two stage CMOS Class E RF power amplifier for ISM(Industrial/Scientific/Medical) Open Band is presented. The power amplifier operates at 2.4GHz frequency, and is designed and simulated with a 0.35um CMOS technology and HSPICE simulator. The power amplifier is simple structure of two stage Class E power amplifier. The design procedure determing matching network was presented. The power amplifier is composed of input stage matching network, preamplifier, interstage matching network, power amplifier, and output stage matching network. The matching networks of input stage and interstage were constituted by pi($\pi$) type and L type respectively. At 2.4GHz operating frequency, and with a 2.5V supply voltage, the power amplifier delivers 23dBm output power to a 50${\Omega}$ load with 39% power added efficiency(PAE).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.117-122
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• 2016

In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.83-88
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• 2007

The reliability characteristics of class-E RF power amplifier are studied, based on the degradation of MOSFET electrical characteristics. The class-E power amplifier operates as a switch mode operation to achieve high efficiency. This operation leads to high voltage stress when MOSFET switch is turned-off. The increase in threshold voltage and decrease in nobility caused by high voltage stress leads to a drop in the drain current. In the class-E power amplifier the effects caused by the degradation of MOSFET drain current is a drop of the power efficiency and output power. But the small inductor in the class-E load network allows the reliability to be improved. After $10^{7}\;sec$. the drain current decreases 46.3% and the PAE(Power Added Efficiency) decreases from 58% to 36% when the load inductor is 1mH. But when the load inductor is 1nH the drain current decreases 8.89% and the PAE decreases from 59% to 55%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.880-886
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• 2007

We have proposed a new "hybrid" envelope elimination and restoration(EER) transmitter architecture using an efficiency optimized power amplifier(PA) and modified bias modulator. The efficiency of the PA at the average drain voltage is very important for the overall transmitter efficiency because the PA operates mostly at the average power region of the modulation signal. Accordingly, the efficiency of the PA has been optimized at the region. Besides, the bias modulator has been accompanied with the emitter follower for the minimization of memory effect. A saturation amplifier, class $F^{-1}$ is built using a 5-W PEP LDMOSFET for forward-link single-carrier wideband code-division multiple-access(WCDMA) at 1-GHz. For the interlock experiment, the bias modulator has been built with the efficiency of 64.16% and peak output voltage of 31.8 V. The transmitter with the proposed PA and bias modulator has been achieved an efficiency of 44.19%, an improvement of 8.11%. Besides, the output power is enhanced to 32.33 dBm due to the class F operation and the PAE is 38.28% with ACLRs of -35.9 dBc at 5-MHz offset. These results show that the proposed architecture is a very good candidate for the linear and efficient high power transmitter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.4
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• pp.51-58
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• 2004

Push-pull structure with balun transformer is presented for load modulation technique which improves the overall efficiency of power amplifier Under the assumption that output impedance of fumed-off amplifier is high, conventional Doherty amplifier is composed of impedance inverter and peaking amplifier, of which operation is controlled by the input power level. In many case, however, impedance of 'off'amplifier is very low due to matching network or parasitic output capacitance. This paper introduces novel load modulation technique which uses low output impedance of 'off'amplifier. Experimental results show that good linearity and efficient!'enhancement of the proposed push-pull structure

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1060-1068
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• 2011

In this paper, Current-Mode Class-D(CMCD) RF Power Amplifier(PA) is designed and implemented at 900 MHz. Conventional CMCD PA has output parallel resonator to reconstruct a fundamental frequency component of the output signal. However the resonator can be removed by connecting inverse class-F PAs because even-harmonic components can be removed by CMCD PA's push-pull structure. Using load-pull, inverse class-F PA with GaN transistors is designed, and CMCD PA with the inverse class-F PA is implemented. The CMCD PA has 64.5 % drain efficiency, 34.2 dBm output power. Comparing with the drain efficiency of a CMCD PA with parallel resonator, the CMCD with the inverse class-F technology has 13.6 % improved drain efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.5 s.108
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• pp.408-415
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• 2006

This paper suggests an improved system-level model of RF power amplifiers(PAs) including memory effects, and validates the suggested model by analyzing the power spectral density of the output signal with a predistortion linearizer. The original three-box(Wiener-Hammerstein) model uses input and output filters to capture RF frequency response of PAs. The adjacent spectral regrowth that occurs in three-box model can be perfectly removed by Hammerstein structure predistorter. However, the predistorter based on Hammerstein structure achieves limited performance in real PA applications due to other memory effects except RF frequency response. The spectrum of the output signal can be predicted accurately using the suggested model that changes a memoryless block in a three-box model with a memory polynomial. The proposed model accurately predicts the output spectrum density of PA with Hammerstein structure predistorter with less than 2 dB errors over ${\pm}30$ MHz adjacent channel ranges for IEEE 802.11 g WLAN signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1262-1270
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• 2007

In this paper, we propose a new distortion cancellation mechanism for a balanced power amplifier structure using the carrier cancellation loop of a feedforward and post-distortion technique. The proposed cross post-distortion balanced linear amplifier can reduce nonlinear components as much as the conventional feedforward amplifier through the output dynamic range and broad bandwidth. Also the proposed system provides higher efficiency than the feedforward. The capacities of power amplifier and error power amplifier in the proposed system are analyzed and compared with those of feedforward amplifier. Also the operation mechanisms of the three kind loops are explained. The proposed cross post-distortion balanced linear power amplifier is implemented at the IMT-2000($f_0=2.14\;GHz$) band. With the commercial high power amplifiers of total power of 240 W peak envelope power fer base-station application, the adjacent channel leakage ratio measurement with wideband code division multiple access 4FA signal shows 18.6 dB improvement at an average output power of 40 dBm. The efficiency of fabricated amplifier Improves about 2 % than the conventional feedforward amplifier.